Multi-threshold CMOS (MTCMOS) has been a proven methodology to reduce leakage power in DSM designs. Reviously lumped sleep transistors were designed for worst case condition, and hence occupied a large area. To reduce the area, Cluster based sleep transistor design was proposed which takes into account simulataneous switching within the circuit blocks. In this paper, we propose an improved method of clustering the sleep transistors by taking on chip decoupling capacitances into account. With the proposed heuristic, we are able to obtain sleep transistor area reduction of 64% with respect to conventional clustering methodology. The leakage current reduction for the circuit blocks is in the order of ZOOOX to 8OOOX with respect to the ones without sleep transistors. We also analyze the effect of the sleep transistor width on the wake-up time of the circuit blocks, which can be used effectively during system design. The experimental results are shown for ISCAS'85 benchmarks.
We present a low-area implementation of an I/Q mismatch compensation (IQMC) circuit that comprises a correction engine and an adaptation engine. The correction engine performs I/Q mismatch compensation in the data path using a filter whose coefficients are updated after a programmable amount of time by a parallel adaptation engine that performs sample-by-sample off-line adaptation. This scheme allows very fast online adaptation while protecting the receiver data path from the degradations caused by a fast converging algorithm. The proposed scheme has been successfully implemented in 90-nm digital CMOS process for a low-IF quad-band GSM transceiver SoC. A single multiplier is used to perform complex multiplications for both correction and adaptation engines, resulting in a 0.025 mm 2 circuit. Image Rejection Ratio in excess of 50 dB is measured that is sufficient for IF frequencies as high as 200 kHz for GSM application.
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