In thls paper, automatlc generation 02 efflcient Instruction code for integrated digital signal processors is addressed. Since these processors are primarily used in real-time applications, lnstructlon code has to meet high quality requlrements. For this reason. we are Interested in generatlng optimal or a t least highly optimized code regarding its execution time. However, in general, conventional compller design techniques do not lead to satisfactory results because signal processors and microprocessors are very different In architecture. The algorithm for automatic lnstructlon code generation presented in this paper Is based on a target machlne description by trellls dlagrams. I t can be applied to generating efficient instruction code for a large number of modern Integrated digltal slgnal processors.
I. INTRODUCI'IONIt Is common practice to specify discrete-the slgnal processing systems by signal flow graphs (SFGs). Frequently, such systems are reallzed by using Integrated dlgital signal processors. To thls end, an appropriate lnstructlon sequence has to be found for computing the respective SFG. In real-time applications, this Instruction code has to be optimized regarding Its execution time.When translating SFGs into instruction code, i t has to be decided In what order the lndivldual operatlons are to be performed, what locatlons intermediate results are to be written to, and what instructlons are to be used. Most modern integrated digital signal processor6 provide hardware t o transfer data by reglster-indirect addressing and to update address registers In parallel to arithmetic or loglcal operatlons. Obvlously, in order to mlnimlze the execution time, both address computatlons and data transfers should be performed in parallel to arithmetic and logical operations a s often a s possible.For this purpose, an appropriate arrangement of the data In memory and allocatlon of address reglsters has to be found depending on the order in which the indlvidual memory locations are referenced.This work is supported by the Fonds zur F6rderung der wissenschaftlichen Forschung. research grant P8692-PHY.Unfortunately, the problem of generating optimal code for directed acyclic graphs (DAGS) is NP-complete even for very simple target machine models 111, i.e., there are only algorithms for finding the optlmal solution whose executlon time depends exponentially on the size of the DAG.Frequently, there Is a very large number of different orders in whlch the indlvidual operatlons of small discrete-time slgnal processlng systems can be carried out [21. A s a consequence, various heuristlc algorithms are proposed generating code for optimized SFG computation, as for example 13-81.SFC decomposition into maximum sized expresslon trees which subsequently are translated separately into optimal Instruction code Is proposed in t91. A versatile translation procedure for Integrated digital slgnal processors with parallel data transfer features is discussed in C101.
AUTOMATIC INSTRUCTION CODE GENERATIONA s mentloned above, In this paper...
Generating optimum data memory layouts and address pointer assignments for digital signal processors are hard combinatorial optimization problems. In this paper, it is shown that for fixed memory layouts and in contrast to traditional heuristic approaches optimum address pointer assignments can be generated easily. The computational complexity depends exponentially just on the number of address pointers. The proposed technique is applied to a large benchmark suite. Experimental results for three address pointers show that optimum solutions can be generated in almost all cases (99.98%) within one second. Since a large number of address pointers may be intractable, an additional heuristic pruning technique with nearly optimum performance is proposed.
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