In this paper the problem of sofmare simulation of the noise distribution in the chip has been considered. On the basis of earlier developed analytical equations the internal electromagnetic noise distribution in the chip with orthogonal and complanar topology of power supply feeding have been obtained. These results can be useful to estimate the trends of the EM noise in the chip and evaluate the most critical area. Further, developer can change the placing of the functional modules in the chip to increase the stability of the designed device to internal noises.
Specific features of ICs parametric optimisation problem are considered in this paper. These specific features are mainly determined by the kind of optimisation model, which consists of different types of optimisation variables, objective functions and functions of constraints. The detailed analysis of combination of different types of optimisation model parts allows us to choose proper optimisation method.
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