Degradation mechanisms accelerated by harsh conditions (high temperature, electrical stress) can affect circuit performances. Submitted to electromagnetic interferences, aged components can become more susceptible, which stirs up questions about the safety level of the final application. Unfortunately, the impact of circuit aging on its susceptibility level remains under evaluated and is not taken into account at circuit design level. This paper presents a first attempt of a modeling methodology aiming at predicting the impact of circuit aging on the susceptibility to electromagnetic interferences. This methodology is applied to model and explain the measured variations of the susceptibility level of phase-locked loop after an accelerated-life test.
We report on the development of coplanar contact pattern for the rf-characterisation of nanoscaled devices. A contact layout exhibiting a low parasitic capacitance is developed using electrostatic field theory calculations. The improved pad-and coupling capacitance has been experimentally verified based on scattering parameter measurements and small signal parameter extraction of a single nanowire transistor.The low-band-gap, high mobility InAs semiconductor is an excellent candidate for high-speed, and lowvoltage electronic devices. In the standard configuration these devices suffer from a low output resistance. A nanowire channel with a wrapped around gate has the potential to offer an optimum gate control because the carriers can not escape into the substrate [1]. An omega shaped top gate is proposed for the easier fabrication of a high speed device while still maintaining a full surrounding of the wire. An outstanding DC performance of an InAs NW-FETs with a SiN x gate dielectric has already been reported [2]. However, the development of an appropriate device circuit model and the determination of its parameters is a challenging task because typical coplanar access structures exhibit a high capacitive load which is about one order of magnitude higher than the intrinsic small signal elements. We report here on the optimisation of a contact pattern with low parasitics suitable for the rf-characterisation of single nanowire transistor devices. Coplanar Contact Pattern: The parasitic elements of the coplanar contact pattern were studied using OPEN and SHORT calibration elements on a s. i. GaAs substrate with an additional 150 nm SiN x layer for improved isolation and a reduced effective dielectric constant. A 50 µm pitch of the coplanar tip was selected reducing the signal-to-ground capacitance of the OPEN. The input-to-output coupling (capacitance C io ) of the OPEN element was subject to detailed investigations using field theory calculations by ADS MOMENTUM. Both simulations and experiments show that a narrower signal line reduces the pad-substrate coupling and a broader ground line towards the transistor position provides a better shielding. This way the coupling capacitance C io is reduced from 1.3 fF down to 0.6 fF. As a result of the lower C io the parasitic forward coupling is reduced by 5 dB at 20 GHz. The negative impact of this design on the lead inductance was studied using a SHORT calibration element. The lead inductance is doubled to 30 pH approximately, which is still negligibly low. RF of single nanowire FET: The InAs nanowires were synthesized by MOVPE using the vapor-liquid-solid growth mode. InAs nanowire FETs were fabricated by removing the wires from the growth substrate onto an insulating host carrier substrate. The contacted nanowires were covered with a SiN x gate dielectric of 30 nm thickness deposited by ECR-CVD at room temperature. Finally, a Ti/Au gate metal was evaporated forming an omega-shaped gate around the nanowire. Various InAs FETs with a Π-gate of the length L G = 1.4 µm were ...
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