Specifications of a holographic memory suitable for a capacity of 10(8) bit are presented. Mathematical calculations show the influence of various system parameters. The storage density is derived as a function of the maximum spatial frequency in the storage material, the aspect ratio of the data input mask, and the crosstalk. In addition, optimizations of the storage density and the optical efficiency of the system are discussed.
in Figs. 3 and 4. This method of fanning-out at both ends of the connecting lines, using IMGs, not only eliminates line reflections and thus improves a system's reliability, but also allows the system to operate correctly at its maximum guaranteed fan-out capacity [3]. MAHMOUD ABDEL-LATE M. J. 0. S T R~ Swiss Federal Inst. Tech. REFERENCES [l] M. Abdel-Latif and M. J. 0. Strutt, "pulse noise immunity and its relationship to propagation-delay-time in high-speed logic integrated curcuits," Arch. Elek. Ueber-[2] -, "Simpk graptucal method to deermine line reflections between high-speed-logic tragung, vol. 23, pp. 571-518, November 1969. [3] -, "Verfahren und Vomchtung NI Vcnneidung von ReBcxionselTekten bei der integratedAbstract-A simple derivation is provided for the steady-state solution of the vector differential equation i=Ax+Bw when the input is a train of impulses.
CdS in the form of a single crystal is a material exhibiting a steep band edge at the green argon wavelength of 0.515 microm. The thermal shift of this band edge is used to modulate the transmittance of a matrix addressed page-composer for binary data presentation. Short switching pulses in the range of 20 / 50 V applied to evaporated transparent heating elements produce within 100 microsec a 70 degrees C temperature shift in a thin CdS-crystal, being the key element of the page-composer. Contrast ratios of the transmittance of better than 800 and optical efficiencies of 50% are easily obtained in 10 / 20-microm thick samples. Fast parallel switching of twenty-five elements using time multiplex heating has been demonstrated with a 5x5 CdS-page-composer. A 16x18 matrix is being fabricated, and the implementation of larger arrays accessible in 1 msec appears feasible.
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