Floating gate interference resulting from capacitive coupling through parasitic capacitors surrounding the floating gate degrades the cell characteristics such as current, speed and cell V th distribution. For the first time, we have introduced the cell characteristics improved using low-k dielectric of gate spacer such as oxide and air gap in 1Gb NAND Flash memory.
For practical application to multi-functional nanoelectronic devices', single electron transistors (SETs) should have controllable and reproducible characteristics. For high temperature operation, recently proposed SET structures have depended on somewhat contingent phenomena such as unintentional potential barriers in quantum wires [l], e-beam irregularity [2] or randomly distributed nanocrystal arrays 131, so that their device characteristics couldn't be predicted. In this work, SETs with sidewall depletion gates on a silicon-on-insulator (SOI) quantum wire have been fabricated by the combination of conventional lithography and VLSI technology, and their properties were investigated. Figure 1 shows a schematic of the fabricated device. Inversion layer in a ptype 45nm-thick SO1 quantum wire channel is formed by the back gate bias (Vu), and two tunnel junctions are formed by the sidewall depletion gate bias (VsG). The charge of electrically formed quantum dot is controlled by the control gate bias ( V , ) .A uniform 30 nm-wide SO1 quantum wire was formed by sidewall patterning method [4] as shown in Fig. qa), which effectively suppressed unintentional potential barriers. Figure 2(b) and 2(c) show the n-type doped polycrystalline silicon sidewall gates on Si wire, which were formed by the sequential LPCVD and the reactive ion etching of polycrystalline silicon on nitride groove. The separation between two sidewall gates (Sx) was designed to be 37 nm (SET1) and 185 nm (SE=), for the high temperature operation and high voltage gain, respectively. Sidewall depletion gate structure has the merit in that it can implement a feature size smaller than the limit of e-beam lithography [5]. Figure 3 shows the control gate dependence of the drain current and the differential conductance of SETl at 77 K. Clear multiple Coulomb oscillation peaks are obtained with the period (AVffi) of 600 mV. This characteristic is superior to the recently published Si based high temperature SETs [2,6] in that many peaks are observed at 77% and IO&W value is maintained as the control gate voltage increases. Gate capacitance of 0.27 aF extracted from AVffi is consistent with that of 0.24 aF estimated from the device geometry. Moreover, AV, is constant as VCG increases. These characteristics stem from the strong controllability of tunnel barriers by VSC, which can be attributed to the 3-dimensional structure of the sidewall depletion gate wrapping Si channel. This is confirmed by 3-dimensional device simulation, as shown in Fig. 4.The size of electrostatically defined quantum dot is invariant in sweeping V , .Considering that, in many cases of previous reports, electrically formed quantum dots were too sensitive to gate bias conditions to maintain the reliable multiple switching performance and showed just a small number of peaks only in a subthreshold region [5, 71, the fabricated SETs are much improved and comparable to SETs by physically formed'quantum dot [6]. Figure 5 shows the drain voltage dependence of the drain current of SETl at 77 K. C...
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