Abstract-Micromachining techniques are being increasingly used to develop miniaturized sensor and actuator systems. These system designs tend to be captured as layout, requiring extraction of the equivalent microelectromechanical circuit as a necessary step for design verification. This paper presents an extraction methodology to (re-)construct a circuit schematic representation from the layout, enabling the designer to use microelectromechanical circuit simulators to verify the functional behavior of the layout. This methodology uses a canonical representation of the given layout on which feature-based and graph-based recognition algorithms are applied to generate the equivalent extracted schematic. Extraction can be performed to either the atomic level or the functional level representation of the reconstructed circuit. The choice of level in hierarchy is governed by the trade off between simulation time and simulation accuracy of the extracted circuit. The combination of the MEMS layout extraction and lumped-parameter circuit simulation provides MEMS designers with VLSI-like tools enabling faster design cycles, and improved design productivity.[682]
Microelectromechanical systems (MEMS) integrating multi-domain sensors and actuators with conventional microelectronic batch fabrication processes are becoming increasingly complex. In order to design systems with large numbers of multi-domain components, we need to use a hierarchical structured design approach, with design at the schematic level instead of the traditional layout representation used in MEMS design. However, since fabrication can only be done from a layout representation, an automatic or manual layout generation from schematic is necessary. It is essential to be able to translate from the layout representation back to the schematic to reason about layout correctness in meeting the schematic’s function as well as to extract geometric parameters for functional simulation. An extraction module is developed which reads in the geometric description of the layout structure and reconstructs the corresponding schematic. This schematic can then be fed to an ordinary differential equation solver or can be compared with the design schematic to validate the correctness of the designed layout. The extraction module also minimizes the number of nodes required to represent the schematic as a netlist. The results presented show the success of the module for some example MEMS designs.
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