Advances of the VLSI technology into the sub-90nm processes, enabling complex CPU designs that work at GHz frequencies pose numerous design and verification challenges.In this invited presentation, we focus on challenges in timing analysis of CPU's working at GHz speeds and sub90nm processes.We start by brief overview of Timing Analysis tool used for intel CPU's and the "shell" timing models used for large blocks and how they integrate into full-chip model. Hierarchical timing is emphasized as key enabler for handling full-chip timing.
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