Border traps and interface traps in HfO2/few-layer MoS2 top-gate stacks are investigated by C–V characterization. Frequency dependent C–V data shows dispersion in both the depletion and accumulation regions for the MoS2 devices. The border trap density is extracted with a distributed model, and interface traps are analyzed using the high-low frequency and multi-frequency methods. The physical origins of interface traps appear to be caused by impurities/defects in the MoS2 layers, performing as band tail states, while the border traps are associated with the dielectric, likely a consequence of the low-temperature deposition. This work provides a method of using multiple C–V measurements and analysis techniques to analyze the behavior of high-k/TMD gate stacks and deconvolute border traps from interface traps.

Two-dimensional transitional metal dichalcogenide (TMD) field-effect transistors (FETs) are promising candidates for future electronic applications, owing to their excellent transport properties and potential for ultimate device scaling. However, it is widely acknowledged that substantial contact resistance associated with the contact-TMD interface has impeded device performance to a large extent. It has been discovered that O2 plasma treatment can convert WSe2 into WO3-x and substantially improve contact resistances of p-type WSe2 devices by strong doping induced thinner depletion width. In this paper, we carefully study the temperature dependence of this conversion, demonstrating an oxidation process with a precise monolayer control at room temperature and multilayer conversion at elevated temperatures. Furthermore, the lateral oxidation of WSe2 under the contact revealed by HR-STEM leads to potential unpinning of the metal Fermi level and Schottky barrier lowering, resulting in lower contact resistances. The p-doping effect is attributed to the high electron affinity of the formed WO3-x layer on top of the remaining WSe2 channel, and the doping level is found to be 2 dependent on the WO3-x thickness that is controlled by the temperature. Comprehensive materials and electrical characterizations are presented, with a low contact resistance of ~528  m and record high on-state current of 320 A/m at -1V bias being reported.

The benefits of O 2 plasma exposure at the contact regions of dual-gate MoS 2 transistors prior to metal deposition for high performance electron contacts are studied and evaluated. Comparisons between devices with and without the exposure demonstrate significant improvements due to the formation of a high-quality contact interface with low electron Schottky barrier (∼0.1 eV). Topographical and interfacial characterizations are used to study the contact formation on MoS 2 from the initial exfoliated surface through the photolithography process and Ti deposition. Fermi level pinning near the conduction band is shown to take place after photoresist development leaves residue on the MoS 2 surface. After O 2 plasma exposure and subsequent Ti deposition, Ti scavenges oxygen from MoO x and forms TiO x . Electrical characterization results indicate that photoresist residue and other contaminants present after development can significantly impact electrical performance. Without O 2 plasma exposure at the contacts, output characteristics of MoS 2 FETs demonstrate nonlinear, Schottky-like contact behavior compared to the linearity observed for contacts with exposure. O 2 plasma allows for the removal of the residue present at the surface of MoS 2 without the use of a high-temperature anneal. A low conduction band offset and superior carrier injection are engineered by employing the reactive metal Ti as the contact to deliberately form TiO 2 . Dual-gate MoS 2 transistors with O 2 plasma exposure at the contacts demonstrate linear output characteristics, lower contact resistance (∼20× reduction), and higher field effect mobility (∼15× increase) compared to those without the treatment. In addition, these results indicate that device fabrication process induced effects cannot be ignored during the formation of contacts on MoS 2 and other 2D materials.

High quality sub-10 nm high-k dielectrics are deposited on top of MoS2 and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. The results show that the Al2O3 buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS2/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. Dual-gate transistors encapsulated in an Al2O3 dielectric demonstrate a near-ideal subthreshold swing of ∼60 mV/dec and a high field effect mobility of 100 cm2/V·s.

The interconnect half‐pitch size will reach ≈20 nm in the coming sub‐5 nm technology node. Meanwhile, the TaN/Ta (barrier/liner) bilayer stack has to be >4 nm to ensure acceptable liner and diffusion barrier properties. Since TaN/Ta occupy a significant portion of the interconnect cross‐section and they are much more resistive than Cu, the effective conductance of an ultrascaled interconnect will be compromised by the thick bilayer. Therefore, 2D layered materials have been explored as diffusion barrier alternatives. However, many of the proposed 2D barriers are prepared at too high temperatures to be compatible with the back‐end‐of‐line (BEOL) technology. In addition, as important as the diffusion barrier properties, the liner properties of 2D materials must be evaluated, which has not yet been pursued. Here, a 2D layered tantalum sulfide (TaSx ) with ≈1.5 nm thickness is developed to replace the conventional TaN/Ta bilayer. The TaSx ultrathin film is industry‐friendly, BEOL‐compatible, and can be directly prepared on dielectrics. The results show superior barrier/liner properties of TaSx compared to the TaN/Ta bilayer. This single‐stack material, serving as both a liner and a barrier, will enable continued scaling of interconnects beyond 5 nm node.