Designing of a reliable digital system is a challenging task because it incorporates testing of circuits at the design time. With this feature the designer can depict testable circuit for transient faults at the design stage. In this paper we have proposed a technique of transient fault injection system with the help of Verilog description based language. The key feature of the fault injection system is pseudo random sequence which is generated through LFSR. Standard LFSR based fault injection system is less efficient in terms of hardware utilization; to reduce hardware of the injection system Berlekamp-Massey Algorithm (BMA) is used. Experimental results show that the proposed technique has a superior performance, compared to existing technique.
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