Research on the prevention of epileptic seizures has led to approaches for future treatment techniques, which rely on the demanding computation of generalized partial directed coherence (GPDC) on electroencephalogram (EEG) data. A fast computation of such metrics is a key factor both for the off-line optimization of algorithmic parameters and for its real-time implementation. Aiming at speeding up the GPDC computations on EEG data, the current paper presents massively parallel computational strategies for implementing the GPDC on many-core architectures. We apply the proposed strategies on commercial and experimental many-core platforms and we compare the results of the computation time of a set of EEG data on the Bulldozer and Ivy Bridge x86_64 serial processors. We test the GPUs of nVidia GTX 550 Ti and GTX 670, which at the best case achieve a significant speedup of 190x and 460x respectively. Moreover, we apply the proposed parallelization strategies on the Single-Chip Cloud Computer (SCC), an experimental processor created by Intel Labs
The current paper introduces a real-time architecture for the computation of the Generalized Partial Directed Coherence (GPDC) of multiple signals. The motivating application is the localization and control of epileptic seizures where hitherto published results shown the effectiveness of exploiting Generalized Partial Directed Coherence to quantify and analyse connectivity and interaction of brain structures. To speed up GPDC computations we develop first, a parallelizing strategy leading to the high performance scalable architecture and second, a low-complexity fixed-point reciprocal square root module. We show that a real-time computation is feasible at a speed of 0.027ms for 16 channels and 1.637ms for 128 channels. Furthermore, the implementation results on Xilinx 7A35T, KC705, VC707, KU115 show that the power requirements are quite modest and allow for the embedded application of the engine
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