The creation of mesa porosity in single damascene structures after patterning has been investigated to facilitate the sealing of the sidewalls by iPVD harriers. The dielectric stack consists of developmental porous SiLK* (v7) resin (*SiLK is a trademark of The Dow Chemical Company) and a chemical vapor deposited hard mask. Porous SiLK (v7) resin was selected since the temperature of vitrification of the material is lower than the temperature of porogen burn out. Creation of meso porosity after patterning results in smooth trench sidewalls, leading to an improved iPVD barrier integrity, as opposed to the conventional process , sequence, which gives rise to large, exposed pores at the sidewall.
IntroductionThe lntemational Technology Roadmap for Semiconductors [ I ] predicts the need for ultra lowk dielectric materials combined with very thin
In this work, the role of stress and shrinkage during the processing of the sub-70nm shallow-trench isolation (STI) structures filled with a spin-on glass (SOG) material containing perhydro-polysilazane is discussed. The stress behavior of this material on blanket and patterned structures are compared. The different parameters for adjusting the stress and their influences on wet-etching properties and uniformity over the wafer are discussed. Finally, the effect of stress on electrical parameters is presented.
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