These days, the security of information has become more vital in data transfer through networks and storages, so everyone knows the importance of data encryption to maintain the confidentiality and privacy of information transmitted across different networks. Image ciphering plays a vital role in avoiding eavesdropping or cracking access to the information that is transferred through networks; therefore, to look after the privacy and security of the information that is transferred on the internet, one of the important methods of security is chosen in this paper, which is “Advanced Encryption Standard”. The Advanced Encryption Standard is chosen in this paper based on the capability of it to secure information and the power of it to immunize information from eavesdropping. A Graphical User Interface (GUI) in Matlab is used as software to implement the Advanced Encryption Standard algorithm and to tests various types of High Definition. This research is focused on experiments on different types of pictures (gray, color and black and white) in high quality and seeing the required time for applying the Advanced Encryption Standard algorithm on these pictures. The results of this paper show the time that is required for ciphering and deciphering different types of pictures.
Network on Chip is one of the most crucial in the development of the networks and routers in new days due to the improvement that make through way of sending huge packets of data and technology and protocol that used for sending the packets between IP cores. Also, the NoC is removed the old ways of technique and protocols of sending packets through routers. The NoC is the most enhanced and efficient in working in parallel ways. Hence, Field Program Gate Array (FPGA) is used in the designing of router that its architecture depending on the NoC. The research proposed in this paper proposed 4x4 nodes router with mesh network that support two-dimensional architecture. A real time test is used for experimental through FPGA and the test verified efficient packets transporting via two array buffers that integrated in the proposed router architecture.
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