To satisfy the intra- and inter-system bandwidth requirements of future data centers and high-performance computers, low-cost low-power high-throughput optical interconnects will become a key enabling technology. To tightly integrate optics with the computing hardware, particularly in the context of CMOS-compatible silicon photonics, optical printed circuit boards using polymer waveguides are considered as a formidable platform. IBM Research has already demonstrated the essential silicon photonics and interconnection building blocks. A remaining challenge is electro-optical packaging, i.e., the connection of the silicon photonics chips with the system. In this paper, we present a new single-mode polymer waveguide technology and a scalable method for building the optical interface between silicon photonics chips and single-mode polymer waveguides.
Optically transparent polymer waveguides are employed for interfacing silicon photonics devices to fibers. The highly confined optical mode in the nanophotonic silicon waveguide is transferred to a fiber-matched polymer waveguide through adiabatic optical coupling by tapering the silicon waveguide. The polymer waveguides are either processed onto the silicon photonics wafer or bonded to individual chips. Fibers are interfaced to the polymer waveguides through butt-coupling. We show polarization and wavelength-tolerant fiber-to-chip coupling loss of less than 3.5 dB across the O-band. The polymer waveguide-to-silicon-chip alignment tolerance is 2 µm for a loss increase of only 1 dB. Reflection losses are well below −45 dB and the scalability to large numbers of channels is demonstrated. These results open a path to broadband and polarization-tolerant optical packaging of silicon photonics devices for ultrahigh bandwidth applications employing wavelength division multiplexing across multiple channels as envisioned for future data-center interconnects. Index Terms-Optical interconnections, optical waveguides, optical polymers, silicon on insulator technology, optical coupling. I. INTRODUCTIONO PTICAL interconnects (OIs) are the enabling technology to sustain the growing performance requirements of both cloud data-center servers and high-performance computers (HPCs) [1], [2]. Compared to electrical interconnects, OIs provide inherent advantages such as a larger bandwidth-distance product, a higher interconnect density, and an improved power efficiency [3].Integrated CMOS silicon (Si) photonics technology can combine optical and electrical functions on a single chip. Singlemode (SM) Si-photonics chips can be scaled to provide high bandwidth density and can cover the reach of the OIs between and within data-centers [4]. All the Si-photonics functional building blocks required for that purpose have already
AI) exploits large datasets to learn how to solve a broad variety of tasks such as text/ image recognition, data clustering, equity pricing, and many others [3] . However, computers based on the Von-Neumann architecture are inefficient in the execution of modern AI workloads, and the required power becomes unsustainable due to the growing volume of data involved.The bottleneck for performance derives from the memory wall. The bandwidth of processors has grown faster than the memory one, with the difference between them diverging exponentially. [4] The energetic inefficiency originates to a large extent from energy-hungry accessing of off-chip memory. [5] With the end of Moore's law approaching [6] and the rise of AI, the quest for alternative computing paradigms has intensified.In-memory computing has emerged as a promising hardware architecture for data-centric applications. It consists of memory cells interconnected in a specific design to locally execute logic or arithmetical operations. [7] The crossbar array is an example of an in-memory computing architecture that raised a strong interest in the electron devices community. In this architecture, the memory elements are positioned at the crosspoint between bitlines and wordlines, [8] as depicted in Figure 1a. When a vector of read voltages (V) is applied on the array elements, the currents (I) establishing at The in-memory computing paradigm aims at overcoming the intrinsic inefficiencies of Von-Neumann computers by reducing the data-transport per arithmetic operation. Crossbar arrays of multilevel memristive devices enable efficient calculations of matrix-vector-multiplications, an operation extensively called on in artificial intelligence (AI) tasks. Resistive random-access memories (ReRAMs) are promising candidate devices for such applications. However, they generally exhibit large stochasticity and device-to-device variability. The integration of a sub-stoichiometric metal-oxide within the ReRAM stack can improve the resistive switching graduality and stochasticity. To this purpose, a conductive TaO x layer is developed and stacked on HfO 2 between TiN electrodes, to create a complementary metal-oxide-semiconductorcompatible ReRAM structure. This device shows accumulative conductance updates in both directions, as required for training neural networks. Moreover, by reducing the TaO x thickness and by increasing its resistivity, the device resistive states increase, as required for reduced power consumption. An electric field-driven TaO x oxidation/reduction is responsible for the ReRAM switching. To demonstrate the potential of the optimized TaO x /HfO 2 devices, the training of a fully-connected neural network on the Modified National Institute of Standards and Technology database dataset is simulated and benchmarked against a full precision digital implementation.
A scalable and tolerant optical interfacing method based on flip-chip bonding is developed for silicon photonics packaging. Bidirectional optical couplers between multiple silicon-on-insulator waveguides and single-mode polymer waveguides are designed and fabricated. Successful operation is verified experimentally in the 1530-1570 nm spectral window. At the wavelength of 1570 nm, the coupling loss is as low as 0.8 dB for both polarization states and the planar misalignment loss is less than 0.6 dB for TE and 0.3 dB for TM polarization in a lateral silicon-polymer waveguide offset range of ± 2 µm. The coupling loss does not exhibit any temperature dependence up to the highest measurement point of 70°C.
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