Pre gate oxide and especially "Double Gate Oxide" cleans are the most critical surface preparation steps in the semiconductor industry. This paper describes the key parameters to perform this kind of operations on a fully integrated single wafer cleaning tool. This switch from conventional batch cleaning tool enables significant defect density reduction and therefore yield enhancement. Nonetheless the main challenge of the double gate oxide clean is the prevention and the control of photo lithography resist lift off during the wet etch. This clean is also composed of two other steps, less critical. Nonetheless special care has been considered in the surface preparation in order to avoid any electrical mobility degradation.
This paper presents the development of 1700V-rated 4H-SiC JBS diodes in the state-of-the-art 6-inch SiC-dedicated foundry, NY-PEMC (New York- Power Electronics Manufacturing Consortium). The critical considerations in developing the SiC JBS diode including the cell optimization, edge termination design, process flow, and unit process developments are discussed in this paper. Static device performances such as forward conduction and reverse blocking behaviors of fabricated 1700V, 20A-rated JBS diode are presented.
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