Hearing is one of the most crucial sense for human beings as it connects them to external world. Hearing loss impairs communication which is an essential human function. Hearing disability has massive negative impact on life, work, physical and emotional well-being as well as relationships and is rated as the third most common health problem affecting relations and quality of life. Hearing aid devices can selectively intensify sound signals in order to suit the hearing characteristics of the patients and is a boon for people with hearing misfortune. However, there is a huge gap between the potential and actual hearing aid users. This work provides a critical look into the various challenges posed by hearing aid users, the comparative of the existing state-of-art hearing devices and throws light on bottlenecks in hearing aid design and performance. Filter bank, being the holy grail of Digital Hearing aid, needs special attention for improving the hearing aid performance. Reconfigurability is the need of the hour for providing flexible and tailormade hearing aids that can suit individual hearing requirements. The paper discusses and gives an in-depth insight into the techniques for reconfigurable Filter bank design for performance augmentationin terms of parameters like Signal quality, Auditory compensation, Computational and Hardware complexity, area, speed, power, etc.
The radio, which has as many as components with programmable devices, was envisioned as future of telecommunication industry by Joseph Mitola in 1991. The traditional, bulky and costly radios are expected to be replaced by a radio in which properties of carrier frequency, signal bandwidth, modulation and network access are defined in software. The key requirements for SDR platforms are flexibility, expandability, scalability, re-configurability and reprogrammability. In SDR, the power consumption, configuration time, hardware usage plays significant role. FPGA has both high speed processing capability and good reconfigurable performance hence FPGA architecture is a viable solution for SDR technology The objective of this paper is to demonstrate simulation and implementation of the PSK modems on FPGA using Partial Reconfiguration. By using Partial Reconfiguration (PR) technique the hardware usage, configuration time and power consumption can be reduced. The PSK modulator and demodulator algorithms are simulated using MATLAB R2013a and implemented on FPGA using Xilinx ISE 14.2 System Generator, PlanAhead, Partial Reconfiguration Tool. The results indicate Partial Reconfiguration design leads to negligible reconfiguration time saving in resource utilization by 55%, in power consumption by 75%. The output waveforms are displayed and analyzed using Xilinx ChipScope Pro. The output waveforms are displayed and analyzed using Xilinx ChipScope Pro.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
customersupport@researchsolutions.com
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.