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Most of researches on wireless sensor network (WSN) are focused on how to reduce energy consumption to increase the network lifetime. There are few researches solving the problem of energy optimization ensuring delay constraint. Whereas, the delay is important factor for applications that require delay-sensitive data. Several works have been published to balance the energy consumption and delay. They achieved many different results but each proposal has certain limitations. Some proposals have high computational and messaging complexity. Some others have not found the optimal solution. In this study, we investigate in finding solution to improve the energy efficiency of sensor nodes satisfying end-to-end delay to transmit data from sensor nodes to sink in multi-hop WSNs. Based on Lagrange relaxation method, we propose an aggregate cost function between energy consumption and delay as well as an efficient method to find the optimal multiplier for that objective function. We provide two algorithms to find paths with least energy consumption while maintaining end-to-end delay requirement from any sensor node to sink. Besides analyzing the complexity and convergence of the algorithm, the simulation results also show that the proposed algorithm achieved good balance between energy consumption and delay compared with the previous proposals.

The delay of the multiplier plays a critical role in many high-speed implementations and processors such as RISC, DSP, and image processing cores, etc. In this paper, a design of unsigned 32-bit multiplier is proposed, aiming to achieve the best timing performance with an appropriate area. The proposed architecture consists of a modified Radix-4 Booth encoder, a modified Wallace Tree adder, and a Carry Look Ahead adder. The design has been verified successfully on DE2-115 and then synthesized to ASIC implementation. The FPGAbased experimental result shows that it has the resources of 1788 ALUTs. The synthesized result occupies an area of 58.28 mm 2 with 4.13 ns total delay (i.e. 242.13MHz maximum frequency).

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Abstract-Research in asynchronous circuit approach has been carried out recently when asynchronous circuits are presented more widely in electronic systems. As they are more important in human life, their correctness should be considered carefully. Although there are some EDA tools for design and synthesis of asynchronous circuits, they are lack of methods for verifying the correctness of the produced circuits. In this work, we are about to propose a verification method and apply it in making a new version of the PAiD tool that can enable engineers to design, synthesize and verify asynchronous circuits. Experiments in verifying circuits have been also provided in this work.