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Silicon photonics holds significant promise in revolutionizing optical interconnects in data centers and high performance computers to enable scaling into the Pb/s package escape bandwidth regime while consuming orders of magnitude less energy per bit than current solutions. In this work, we review recent progress in silicon photonic interconnects leveraging chipscale Kerr frequency comb sources and provide a comprehensive overview of massively scalable silicon photonic systems capable of capitalizing on the large number of wavelengths provided by such combs. We first consider the high-level architectural constraints and then proceed to detail the corresponding fundamental device designs supported by both simulated and experimental results. Furthermore, the majority of experimentally measured devices were fabricated in a commercial 300 mm foundry, showing a clear path to volume manufacturing. Finally, we present various system-level experiments which illustrate successful proof-ofprinciple operation, including flip-chip integration with a codesigned CMOS application-specific integrated circuit (ASIC) to realize a complete Kerr comb-driven electronic-photonic engine. These results provide a viable and appealing path towards future co-packaged silicon photonic interconnects with aggregate perfiber bandwidth above 1 Tb/s, energy consumption below 1 pJ/bit, and areal bandwidth density greater than 5 Tb/s/mm 2 .

Perturbations to the effective refractive index from nanometer-scale fabrication variations in waveguide geometry plague high index-contrast photonic platforms; this includes the ubiquitous sub-micron silicon-on-insulator (SOI) process. Such variations are particularly troublesome for phase-sensitive devices, such as interferometers and resonators, which exhibit drastic changes in performance as a result of these fabrication-induced phase errors. In this Letter, we propose and experimentally demonstrate a design methodology for dramatically reducing device sensitivity to silicon width variations. We apply this methodology to a highly phase-sensitive device, the ring-assisted Mach–Zehnder interferometer (RAMZI), and show comparable performance and footprint to state-of-the-art devices, while substantially reducing stochastic phase errors from etch variations. This decrease in sensitivity is directly realized as energy savings by significantly reducing the required corrective thermal tuning power, providing a promising path toward ultra-energy-efficient large-scale silicon photonic circuits.

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We report a novel process variation-aware compact model of strip waveguides that is suitable for circuit-level simulation of waveguide-based process design kit (PDK) elements. The model is shown to describe both loss and-using a novel expression for the thermo-optic effect in high index contrast materials-the thermo-optic behavior of strip waveguides. A novel group extraction method enables modeling the effective index's (n eff ) sensitivity to local process variations without the presumption of variation source. Use of Euler-bend Mach-Zehnder interferometers (MZIs) fabricated in a 300 mm wafer run allow model parameter extraction at widths up to 2.5 µm (highly multi-mode) with strong suppression of higher-order mode excitation. Experimental results prove the reported model can self-consistently describe waveguide phase, loss, and thermooptic behavior across all measured devices over an unprecedented range of optical bandwidth, waveguide widths, and temperatures.