Insulated gate bipolar transistor (IGBT)-based pulsewidth modulation (PWM) inverters are commonly used in inductive load circuits such as motor control. During clamped inductive load turn off of the IGBT, high-power losses occur during two phases. Due to the large inductive motor load, the voltage across the IGBT rises to the bus voltage while carrying the full-rated current. In the second phase, the current decreases as the IGBT goes into its forward blocking mode. In this paper, the turn-off process during the first phase is analyzed in detail for the first time. A simple analytical model has been derived, based upon the initial steady-state minority carrier distribution, which allows predicting the rate of rise of the voltage during this time period where the collector current remains constant. The predictions of the analytical model are in excellent agreement with results obtained from two-dimensional (2-D) numerical simulations over a broad range of minority carrier lifetime values. This analytical model provides a good estimate (within 10%) of the power losses incurred during the first phase of turn off.
Maximum Power Point Tracking MPPT) for solar panels is critical for space applications where power saving gets the first priority with the availability of limited resources. Of the available methods for MPPT, the Perturb and Observe (P&O) method is accurate and simple to implement. In the MPPT design choosing the sampling time and duty cycle step size is important which determines its predictable operation during rapidly varying irradiance conditions. The paper talks about the state of the art design of MPPT converters with a digital closed loop control. A modular software programming algorithm was used which supports a "Plug and Play" feature. The detailed implementation of a MPPT converter for lOW solar panel using Texas Instruments TMS320F2808 Digital Signal Controller is shown in this paper.
Modern processers have the capability of indicating the power state of the processor to the Voltage Regulator (VR) PWM controller so that it can change its operating state to maximize efficiency at light loads and to flatten out its efficiency curve for idle power reduction. The CPU worst case assert and de-assert frequency can be very high for the PWM controller and for the VR to follow. Thus for the VR to take advantage of the low power state signal from the CPU, the signal has to be passed through an analog/digital low-pass filter. The optimum frequency for this filter design is determined in this paper. This filtered frequency with which the VR drops its phases optimizes the overall efficiency of the system. The experimental results are given for a four-phase VRM. It is also shown in this paper that the transient efficiency is as vital as the steady state efficiency considering the load profile of modern CPUs.
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