International audienceMotion estimation (ME) is one of the most time-consuming parts in video encoding system, and significantly affects the output quality of an encoded sequence. In this paper, we present hardware implementation of the Large Diamond Parallel search algorithm. This hardware is designed to be used as part of a complete H.264 video coding system. This architecture is simulated and tested using VHDL and synthesized using Altera Quartus II version 5.1. Also, This architecture presents minimum latency, maximum throughput, full utilization of hardware resources and combining both pipelining and parallel processing techniques. The VHDL code is verified to work at 100 MHz in ALTERA Stratix II FPGA
Entropy coding is a fundamental stage in all video compression algorithms in terms of compression efficiency and error resilience. In this paper we propose and optimize a Digital Signal Processor (DSP)-based implementation of the CAVLC tools for the H.264 Baseline encoder. As result, we have been able to generate the bitstream and supply bit rate result: the LETI encoder is able to achieve high compression performance when proposing interesting video quality.Index Terms------H.264/AVC, CAVLC, TMS320C6416 DSP.
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