Traditional non-volatile flash memories cannot support simultaneous read while write (RWW) i.e. read while pmgramming or erasing the device 111. This shortcoming is addressed by a hardware boundary that divides a flash memory map into 2 elear-eut segments that support simultaneous RWW operations. In this scenario, one segment can be used for the code and the other segment can be used for data. This approach does not allow users to choose the optimal size of the code and data partitions for their particular applications. The use of flash memory as a medium for code+data storage places additional demands on the traditional architecture. The above limitations show the need for truly flexible multi-partition memory architecture.This flash memory is a truly flexible RWW device that allows the memory to be divided into any number of partitions, in this case, each 4Mb, which allows simultaneous RWW operations. This flexible multi-partition architecture allows two processors to interleave code operations while program and erase operations take place in the background. Figure 1 shows the chip plan for the device. The RWW functionality is achieved by separating the write and read paths of the device. The write and read status of each partition is stored in a state machine. The user changes the write and read status by issuing commands to the device. Figure 2.3.1 also shows some of the possible RWW scenarios for the device in a tabular format. The device allows reads in one partition whilk writing in another partition. As shown in Figure 1, the device is partitioned into 16 4Mb partitions. Far example, the user may start a write operation in one of the 16 partitions and while the device is writing to that partition, the user can read the array, the signature or the status in any of the other 15 partitions. Figure 2.3.2 shows waveforms of a read while programming operation where a selected wordline and hitline are a t program voltages in one partition while another set of selected wardline and bitline are a t read voltages in another partition. This example illustrates the full capability of a truly flexible RWW architecture in which a user can seamlessly access data across various partition boundaries.The device provides a n initial access time of 40ns for the first word followed by l0ns access time for the subsequent words in its default four-word page made. This results in an average asynchmnous access time of 18ns per word. 18ns is achieved using address transition detection (ATD) to control the entire read operation. The sensing architecture works with a two-stage dynamic latch-type sense amplifier. Figure 2.3.3 shows the RWW sensing architecture. Figure 2.3.4 shows a dctailed implementation of the sensing architecture. Refer to Figure 2.3.5 for the following read operation example. After an address transition is detected a t T1, a n initial master pulse begins the read cycle. Subsequent pulses enable each stage of the read circuits. The first pulse enables the ward line a t n. The second pulse connects the bit lines t...
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