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Automatic number plate recognition (ANPR) systems are becoming vital for safety and security purposes. Typical ANPR systems are based on three stages: number plate localization (NPL), character segmentation (CS), and optical character recognition (OCR). Recently, high definition (HD) cameras have been used to improve their recognition rates. In this paper, four algorithms are proposed for the OCR stage of a real-time HD ANPR system. The proposed algorithms are based on feature extraction (vector crossing, zoning, combined zoning, and vector crossing) and template matching techniques. All proposed algorithms have been implemented using MATLAB as a proof of concept and the best one has been selected for hardware implementation using a heterogeneous system on chip (SoC) platform. The selected platform is the Xilinx Zynq-7000 All Programmable SoC, which consists of an ARM processor and programmable logic. Obtained hardware implementation results have shown that the proposed system can recognize one character in 0.63 ms, with an accuracy of 99.5% while utilizing around 6% of the programmable logic resources. In addition, the use of the heterogenous SoC consumes 36 W which is equivalent to saving around 80% of the energy consumed by the PC used in this work, whereas it is smaller in size by 95%.

Automatic Number Plate Recognition (ANPR) systems have become widely used in safety, security, and commercial aspects. A typical ANPR system consists of three main stages: Number Plate Localization (NPL), Character Segmentation (CS), and Optical Character Recognition (OCR). In recent years, to provide a better recognition rate, High Definition (HD) cameras have started to be used. However, most known techniques for Standard Definition (SD) are not suitable for real-time HD image processing due to the computationally intensive cost of processing several-folds more of image pixels, particularly in the NPL stage. In this paper, algorithms suitable for hardware implementation for NPL and CS stages of an HD ANPR system are presented. Software implementation of the algorithms was carried on as a proof of concept, followed by hardware implementation on a heterogeneous System on Chip (SoC) device that contains an ARM processor and a Field Programmable Gate Array (FPGA). Heterogeneous implementation of these stages has shown that this HD NPL algorithm can localize a number plate in 16.17 ms, with a success rate of 98.0%. The CS algorithm can then segment the detected plate in 0.59 ms, with a success rate of 99.05%. Both stages utilize only 21% of the available on-chip configurable logic blocks.

There are several algorithms and methods that could be applied to perform the character recognition stage of an automatic number plate recognition system; however, the constraints of having a high recognition rate and real-time processing should be taken into consideration. In this paper four algorithms applied to Qatari number plates are presented and compared. The proposed algorithms are based on feature extraction (vector crossing, zoning, combined zoning and vector crossing) and template matching techniques. All four proposed algorithms have been implemented and tested using MATLAB. A total of 2790 Qatari binary character images were used to test the algorithms. Template matching based algorithm showed the highest recognition rate of 99.5% with an average time of 1.95 ms per character

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