The work consists in the development of hardware-oriented methods for restoring the structure of the target word. The reconstruction storation is performed by constructing its prefix and suffix from a set of private words, understood as patterns. The reconstruction of the unknown word is performed by formation its prefix and suffix from a set of private words, understood as standards. The goal is to reduce the recovery time of the structure of the target word by parallel processing of pairs of words stored in the matrix of the original partial words. Solution method. The method consists of 4 stages. They include the stage of parallel processing of fragments of pairs of words for their intersection and selection of mismatched characters. These characters are candidates for the current prefix and suffix characters. A distinctive feature of the proposed method is the hardware support of the main operations in the form of a homogeneous computational PIM structure and the use of a string data structure rather than tuples. For a tuple, the minimum work item is a single character, so the processing of an m-tuple is sequential element-by-element. For a word, the minimum work item is a string of characters that can be processed in parallel without losing the generality of properties. The meaning of the PIM structure is the integration of register memory blocks and functional units for comparing character strings, which allows parallel processing of an array of elements without wasting time on intermediate transfers. Results and discussions. Algorithms are modeled based on the known method and the developed method, using variable parameters: the number of private words, the length of the private word, the cardinality of the alphabet. Modeling showed that the developed method has a time advantage from 1,25 to 9,97. Conclusion. The developed hardware-oriented method for restoring the target word based on the analysis of a set of private words that have a structural relationship with each other has shown its temporal efficiency with increasing values of the varied parameters. This property testifies to the prospects of using the method in search-analytical problems of a real level of complexity.
In the context of the rapid growth of various areas of the Internet of things, there is currently no unified approach to building networks based on low-power Wide-area Network (LPWAN) wireless networks, taking into account the general requirements for them as automated control systems (ACS). There are the following areas of use of the Internet of things: industry and production; transport and transportation; control of the technical condition of building structures, air quality, background noise and energy consumption; waste management; smart Parking and providing data on traffic jams; smart street lighting and use in everyday life. Networks based on LoRaWAN technology provide low-cost energy-efficient wireless communications for modern ACS in a variety of industries. It is cost-effective for designing hardware and software for telemetry and controlling, such as a system of control and monitoring engineering systems of buildings and facilities (SMES) and automated outdoor lighting control systems. The article presents a structural and functional analysis of approaches to the construction of hardware and software complex elements based on LoRаWAN, taking into account the specifics and logic of the SMES and ASUS. It also provides calculations of network bandwidth and capacity for a single LoRaWAN gateway in a different mode of operation of ACS. A parametric analysis of existing implementations was carried out to design the management server (SU), which is the main element of the LoRaWAN network. The results allowed to obtain seventeen indicators that determine the functionality of a network server (NS). Network server software development. Major structures and the mechanisms of interaction of its elements are determined during the process of designing the original implementation of NS software.
The research consists in the development of hardware pattern search methods that use the principles of shared access and parallel data processing inherent in associative memory. Reducing the search time is achieved through the formation and parallel processing of a binary (characteristic) matrix of comparisons of pattern symbols and text. A composite pattern has been introduced, it allows flexible description of search terms. The characteristic matrix is in the form of a parallelogram; it consists of rows shifted to the right, starting from the first row. This form allows you to conduct a parallel search for simple and composite patterns on the diagonal elements of the matrix. The developed method supports hardware search in the characteristic matrix. It is distinguished by the simultaneous consideration of local and distributed relationships between the elements of the diagonals and rows of the matrix. Separate calculation of starting values along the diagonals of the matrix allows you to independently search for two types of samples by calculating in the cells of the diagonals of the characteristic matrix of two output search functions. The method has linear time and quadratic hardware complexity. The clock pulse duration is determined by the sum of the delays of the comparison circuit for a pair of symbols, a D-flip-flop and a two-input element I. The homogeneous structure of the matrix search device, the use of standard operations allow the device to be implemented on a promising FPGA element base, which determines its use in high-performance systems for processing and transmitting heterogeneous information.
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