This article presents guidelines for designing the power supply blocks of RF oscillators. To preserve their spectral purity, the requirements on the noise and ripple of the supply voltage are firstly evaluated based on the oscillator supply pushing factor and the oscillator Figure-of-Merit (FOM). Those specifications are then employed to design and estimate the power efficiency of an analog low-dropout regulator (LDO) and a switched-capacitor DC-DC converter. As a proof of concept, a 2:1 or 3:2 switched-capacitor DC-DC converter is implemented and directly connected to our previously published 4.9 − 5.5 GHz LC oscillator. The converter provides a 1 V supply voltage with a noise ≤ 0.9 nV/ √ H z at 1 MHz and does not affect the inherent phase noise of the oscillator. The ripple amplitude of the converter is 30 mV while its effect is suppressed by the spur reduction block embedded in the oscillator.
In this paper, we propose a new scheme to directly power a 4.9-5.6 GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3-2.2 V and <2 mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is <1.5 nV/ √ Hz, which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65 dBc under the 30 mV pp ripple of the converter.
In this paper, a power-efficient multiphase Recursive Switched Capacitor (RSC) converter is presented. Conventionally, RSC converters are used to obtain many different output voltages from a fixed input voltage. Here, the converter provides a fixed output voltage of 1 V at 1 mA from an input voltage ranging from 1.4 V to 4.5 V. It has one programmable stage (2 : 1 or 3 : 2) followed by four 2 : 1 stages. Contrary to most conventional topologies, depending on the input voltage, not all the stages are always deployed. This allows to increase the power efficiency of the whole architecture. The flying capacitance of the nonactivated stages is transferred to the activated ones. Hence, for any given input voltage, 100% of the on-chip capacitance is always used for the conversion. For a general 2 : 1 topology, an analytical analysis of the power losses is carried out and the impact of the overdrive voltage of the switches on the power efficiency is quantified. A novel gate-driver technique for the switches involved in the conversion is proposed. It ensures an optimal overdrive voltage of the transistor, irrespective of its source and drain potentials. The 16-phase interleaved converter employs a charge recycling technique and uses a total on-chip capacitance of 3 nF. The RSC converter is designed to be implemented in a standard 40 nm CMOS process which offers a capacitor density of approximately 2 nF/mm 2. Circuit simulations over the whole input voltage range show a power efficiency never lower than 54% with a peak value of 92.7%.
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