A novel approach for the design of an asynchronous comparator implemented in standard digital CMOS technology for power supply applications is presented. The 1mV-sensitivity comparator is designed for asynchronous event detection, featuring a multi-stage topology for power efficiency and minimum propagation delay. It also contains a mixed-mode offset compensation architecture that allows full compensation in a single cycle. The comparator has been successfully used in the design of a very high frequency, 300mA multimode PWMPSM (Pulse Width Modulatioflulse Skipping Mode) buck converter. The comparator is able to operate with a supply voltage as'low as 2.4V. Operating with a 3.6V supply, under typical operating conditions, the comparator features a 19ns delay consuming 161pW.
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