The paper considers neural net models and training and recognizing algorithms with base neurobiologic operations: p-step autoequivalence and non-equivalenc The Modified equivalently models (MEMs) of multiport neural net associative memory (MNNAM) are offered with double adaptive -equivalently weighing (DAEW) for recognition of 2D-patterns (images). It is shown, the computing process in MNNAM under using the proposed MEMs, is reduced to two-step and multi-step algorithms and step-by-step matrix-matrix (tensor-tensor) procedures. The given results of computer simulations confirmed the perspective of such models. Besides the result was received when MNNAM capacity on base of MEMs exceeded the amount of neurons.
The conception of construction of the family of the offered optoelectronic photocurrent reconfigurable (OPR) universal or multifunctional logic devices (ULD) consists in the use of a current mirrors realized on 1.5µm, 0.35µm, 65nm technology CMOS transistors. Presence of 44 transistors, 1÷5 photo-detectors makes the offered circuits quite compact and allows their integration in 1D and 2D arrays. The simulation results of the OPR ULD on the 1.5µm, 0.35µm, 65nm technology CMOS transistors showed that the level of logical unit can change from 20nA, 50nA, 500nA 1µA to 10µA for low-power consumption variants and from 20-500nA to 1-10µA for high-speed variants. The base cell of the OPR ULD consist of a small amount of photo diodes, transistors and LED have low power consumption <1µW-5mW. Modeling of such cells in OrCad is made. It is confirmed that all set of possible functions will be realized such OPR ULD by a simple photo-tuning with 10 12 op/s.
rays of optical detectors and light emitters which send and receive data directly out from the chip area. Honeywell has developed such devices with VCSEL diodes (vertical surface emitting laser diodes) and metal-semiconductor-metal photo-detectors in research project [4]. This allows the realization of stacked 3-D chip architecture in principle. The main problems are not the manufacturing and operating of single devices but the combination of different passive optical elements with active optoelectronic and electronic circuits in one system. This requires sophisticated mounting and alignment techniques which allow low mechanical tolerances and the handling of thermal problems. At present the situation for smart detector circuits is much easier. They can be regarded as a subset of OE-VLSI circuits because they consist only of arrays of photo-detectors with corresponding evaluation circuit for analogue to digital converting. Optical detectors based on PN or PIN photodiodes can be monolithically integrated with digital electronics in silicon what simplifies the design enormously compared with OE-VLSI circuits that in addition contain sender devices realized in GaAs technologies. Furthermore smart detector circuits can be manufactured in nearly every semiconductor fabric. Smart detectors or smart optical sensors show a great application field and market potential. Therefore our approach favors a smart pixel like architecture combining parallel signal detection with parallel signal processing in one circuit. Each pixel has its own PE what guarantees the fastest processing.
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