Semantic Web technologies have contributed mainly to organize the knowledge and to search about this organized knowledge. One of the most complex search is to know if two entities are related within a ontology. These are called Semantic Associations, which have been classified using operators: -path, -join and -iso. Then, a -query will solve any of them. Studies about this area offer low performance execution times, but others increase the performance with pre-processing, making use of complex structures in memory. In this paper, we present semantic associations and analyze related studies. We focus on design a simplified representation of the ontology that facilitates the navigation and reduce the algorithms complexity to solve these operators, starting from the first of them: -path.
Abstract. Semantic Web technologies have contributed mainly to organize the knowledge and to search about this organized knowledge. One of the most important and complex kinds of search is to know if two entities are related within an ontology. These are called Semantic Associations, which have been classified using ρ operators: ρ-path, ρ-join and ρ-iso. Then, a ρ-query will solve any of them.Studies about this area offer low performance execution times, while others increase the performance with pre-processing using complex structures in memory.We focus on design of a simplified representation of the ontology that facilitates the graph traversal and reduces the algorithms complexity to solve these operators, starting from the first of them: ρ-path. We propose a topology labeling: we create a tree structure and identify each node with an interval index besides the level of root dependence. We will leave some space within the interval to manage future ontology modifications.To validate this technique we will create ontologies of the order of thousands to 10000 nodes and a framework test with the implementation of the technique proposed in this paper. We will implement other techniques in order to compare execution times and performance.
In this paper is described an embedded system for face identification. The system, running on FPGA, is built around LEON3 processor and consists of several IP (Intellectual Property) modules designed as AMBA bus peripherals. The face detection is accelerated with the help of a hardware module while the face recognition is entirely executed in software. The face detection hardware accelerator module is reconfigurable and can share its internal resources (memory, multiplier, integer square root unit) with the LEON3 processor. The system has been designed on the criteria of resources optimization, low power consumption and improved operation speed.
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