Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Internet traffic. With everincreasing ruleset size and line speed, the task of implementing wire speed packet classification with reduced power consumption remains difficult. Software approaches are unable to classify packets at wire speed as line rates reach OC-768, while state of the art hardware approaches such as TCAM still consume large amounts of power. This paper presents a low power architecture for a high speed packet classifier which can meet OC-768 line rate. The architecture consists of an adaptive clocking unit which dynamically changes the clock speed of an energy efficient packet classifier to match fluctuations in traffic on a router line card. It achieves this with the help of a scheme developed to keep clock frequencies at the lowest speed capable of servicing the line card while reducing frequency switches. The low power architecture has been tested on OC-48, OC-192 and OC-768 packet traces created from real life network traces obtained from NLANR while classifying packets using synthetic rulesets containing up to 25,000 rules. Simulation results of our classifier implemented on a Cyclone 3 and Stratix 3 FPGA, and as an ASIC show that power savings of between 17-88% can be achieved, using our adaptive clocking unit rather than a fixed clock speed.

SUMMARYA recent paper introduced a novel and efficient scheme, based on the transmission line modelling (TLM) method, for solving steady-state convection-diffusion problems. This paper shows how this onedimensional scheme can be adapted to include reaction and source terms and how it can be implemented with non-equidistant nodes. It introduces new ways of calculating the necessary model parameters which can improve the accuracy of the scheme, shows how steady-state solutions can be obtained directly, and compares results with those from two finite difference (FD) methods. While the cost of implementation is higher than for the FD schemes, the new TLM scheme can be significantly more accurate, especially when convection dominates.

SUMMARYThis paper describes how the lossy transmission line modelling (TLM) method for diffusion can be extended to solve the convection-diffusion equation. The method is based on the correspondence between the convection-diffusion equation and the equation for the voltage on a lossy transmission line with properties varying exponentially over space. It is unconditionally stable and converges rapidly to highly accurate steady-state solutions for a wide range of Peclet numbers from low to high. The method solves the non-conservative form of the convection-diffusion equation but it is shown how it can be modified to solve the conservative form. Under transient conditions the TLM scheme exhibits significant numerical diffusion and numerical convection leading to poor accuracy, but both these errors go to zero as a solution approaches steady state.

Abstract-As line rates increase, the task of designing high performance architectures with reduced power consumption for the processing of router traffic remains important. In this paper, we present a multi-engine packet classification hardware accelerator, which gives increased performance and reduced power consumption. It follows the basic idea of decision-tree based packet classification algorithms, such as HiCuts and HyperCuts, in which the hyperspace represented by the ruleset is recursively divided into smaller subspaces according to some heuristics. Each classification engine consists of a Trie Traverser which is responsible for finding the leaf node corresponding to the incoming packet, and a Leaf Node Searcher that reports the matching rule in the leaf node. The packet classification engine utilizes the possibility of ultra-wide memory word provided by FPGA block RAM to store the decision tree data structure, in an attempt to reduce the number of memory accesses needed for the classification. Since the clock rate of an individual engine cannot catch up to that of the internal memory, multiple classification engines are used to increase the throughput. The implementations in two different FPGAs show that this architecture can reach a searching speed of 169 million packets per second (mpps) with synthesized ACL, FW and IPC rulesets. Further analysis reveals that compared to state of the art TCAM solutions, a power savings of up to 72% and an increase in throughput of up to 27% can be achieved.

Packet classification algorithms are increasingly being used to provide security and Quality of Service guarantees. These algorithms are usually implemented on power hungry programmable network processors, which are used in devices such as core routers and firewalls. This paper compares the energy used by five best-known algorithms Recursive Flow Classification, HiCuts, HyperCuts, Extended Grid-of-Tries with Path Compression and Tuple Space Search with Pruning. It does this by measuring the energy used to build the search structure during preprocessing for each of the five algorithms and the average energy taken to classify a packet. To do this we implemented all five algorithms in C code and used a microarchitectural power simulation tool called Sim-Panalyzer to estimate the power dissipated by the five algorithms while running on a SA 100 StrongARM RISC processor similar to the type found on many of today's programmable network processors.