We describe and evaluate a template
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is required, including high-level cache simulation. We propose to perform this cache simulation by defining a metric to represent memory behavior independently of cache structure and back-annotate this into the original application. While the annotation phase is complex, requiring time comparable to normal address trace based simulation, it need only be performed once per application set and thus enables simulation to be sped up by a factor of 20 to 50 over trace based simulation. This is important for embedded systems, as software is often evaluated against many input sets and many architectures. Our results show the technique is accurate to within 20% of miss rate for uniprocessors and was able to reduce the die area of a multiprocessor chip by a projected 14% over a naive design by accurately sizing caches for each processor.
Parallel Programmable Systems-on-a-chip (PP-SoC) data communication or synchronization; parallelism is autoare quickly becoming the de facto architecture for high-matically extracted by the underlying architecture. We believe performance embedded systems. The programming of these that this architecture addresses the most difficult problem with systems is a challenge that often increases the cost of system today's PP-SoCs: programmabili development. The Multi-Level Computing Architecture (MLCA) promises to address this programmability challenge by supportIn this paper, we describe the MLCA architecture and its ing a supersealar coarse-grain parallel programming model. In programming model. We describe the compiler support that is this paper, we describe the MLCA and its programming model. needed for this unique architecture. We give an experimental We provide an overview of the compilation environment we are evaluation of the architecture using realistic multimedia applideveloping for this architecture. We present an evaluation of catnanapoty of the MLCA cmplermeduct the MLCA and its compiler support using realistic multimedia cations and a prototpe of the MLCA compiler. We conduct applications on a simulator and on an FPGA prototype of the this evaluation on both a simulator of the MLCA and on MLCA. The results indicate the viability of this architecture for an FPGA prototype implementation of the architecture. The multimedia applications. results indicate that scaling performance can be obtained for realistic applications using the prototype compiler.The remainder of this paper is organized as follows. Sec-A de facto architecture that has emerged in the embedded tion II describes the MLCA and its programming model and systems market is that of a parallel programmable System-constructs. Section III gives an overview of the MLCA comon-a-Chip (PP-SoC): an integrated design that incorporates piler and the optimizations it performs. Section IV presents our into a single chip multiple programmable cores and various experimental evaluation of the architecture. Finally, Section V custom or semi-custom blocks and memories. This paradigm gives some concluding remarks. allows the reuse of pre-designed cores, thus amortizing the design cost of a core over many system generations. Today, II. THE MLCA there exists several commercial PP-SoCs, including ones by Daytona [1], [2], picoChip [3], Philips [4], [5] and Cradle The MLCA [7] is a novel 2-level hierarchical architecture, Technologies [6]. aimed at parallel SoCs and primarily intended for multimediaHowever, the programming of PP-SoCs remains a chal-applications. The lower level consists of multiple processing lenge. Programming systems with multiple processors poses units (PUs), and the upper level of a controller that autotasks (e.g., partitioning, synchronization, and communication) matically exploits parallelism among coarse-grain units of that are more complex and time-consuming than ones posed computation, or tasks. A PU can be a full-fledged processor by single-proc...
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