This sub-0.5pVMl3 data retention DRAM with relaxed junction biased (RJB), plate-floating leakage monitming E"), and VBB biased pull down word line driver (PDWD) extends retention time ( T A about 3-times and reduce r e h s h current (I& to G.4pVMB. In addition, agate-receivedVBB detector (GRD) and dynamicallycontrolled reference generators (DCRG) reduce dc retention current (h) to 50.1pNMB. This DRAM allom a20MB RAM disk to retain data for 2.6 years with a single button-shaped 1SOmAh lithium battery and can be substituted for SRAM.The cell-leakage (I,J strongly depends on the storage-node voltage (V, ). For example, the & at VN=3.6V is 3-times larger than that of VN=1.8V. Thus, to extend the Tm, the RJB scheme shown in Figure 1 is used. This shifts VN to a lower potential (< %Vcc), in which the junction bias (V, ) is reduced to suppress & to 1/3 the conventional level. When the burst rehsh is finished in the selfrefresh mode, the pause period (Tp) starts, and the VN shifts down by the %Vcc and rests there. After the Tp, the V, goes back to a higher detectable zone ("it), for fast stable sense-amplifier operation. The shift-dodup of the V , is realized by controlling the pull-down/up of the cell-plate voltage(V&. Since the RJB scheme reduces the V, while maintaining negative biased-VBB, the I/O undershoot injection no longer occurs even without a costly triple-well process.A design issue in the RJB scheme is to prevention of low data h m compressingbetweenV,andVNwhentheVmis pulleddownhm %Vcc to Vss. The negative V,,-biased word-line (WL) controlled by PDWD allows the cell-transistor to be turned off and keeps the V, floating even if the V, shifts down to the negative potential (VBBSV&Vss). The PDWD pulls the unseleded WLe down to the VBB level by using the level-shifter Cv, to VBB! that includes the high-VT (2.0V) nMOS circuit. To verify eff&veness of the RJB scheme, the Tm of the 16Mb DRAM chip is measured as shown in Figure 2. The Tm can be extended to 2.7s at Vce=3.6V, Ta=75"C and VB,=-1.3V. This is about 3-times longer than for the conventional case El].Another important design issue in realizing ultra-low IRC, is how the pause period (Tp) of the self-refresh timer can be controlled to monitor an actual TRT that strongly depends on the bad cells that constitute < 0.01% of the chip. In fact, the I, of bad cell is 230times larger than the normal I, and results in 30-times faster falling (F,) of the V, . The PFM scheme accelerates the F, of the monitored V, , of which may be the normal cell, nearby the same level as the bad cell, so the ", of the chip can be monitored exactly. The PFM scheme shown in figure 3 features as follows: 1) When the V, is monitored, the plate-node (VmJ of dummy cells are floating so that the Fsp of V, can be accelerated owing to reduction of the effective cell capacitance caused by the serially connected parastic and junction capacitance. In fact, the F, of the V, can be accelerated by aO-times, compared with the fixed-plate case as shown in Figure 4(a) 121.2) When the V, drops to the re...
