One of the most important properties of Discrete Cosine Transform (DCT) is high power compaction, due to this property DCT is used for coding, image processing, image compression etc. The DCT application can be speed up by Signed Discrete Cosine Transforms (SDCT). The SDCT is the modification approximates of the DCT. In this paper by proposing signum function we proposed a flow diagram of algorithm and its architecture by considering 8 point transforms.
In this paper, we have suggested a simple scheme for prime-factor decomposition of Inverse Discrete Sine Transform (IDST) and systolic mesh architecture for its efficient implementation. In the systolic architecture the transposition of the intermediate matrix is avoided in this structure by orthogonal processing during the pair of matrix multiplication i.e., if the processing for the first matrix multiplication takes place along X-direction, the processing for the second matrix multiplication is carried out along Y-direction. Due to this feature, the systolic architecture is highly compact, offers saving for transposition hardware and at the same time yields high throughput with less latency. The proposed systolic architecture has very less area complexity, less computation time and very high VLSI performance measures compared with existing structures. Due to orthogonal nature of the Discrete Sine Transform (DST), the forward transform may however be realized by the transpositions of the inverse transform.
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