This paper presents an e cient method for state classi cation of nite state Markov c hains using BDD-based symbolic techniques. The method exploits the fundamental properties of a Markov c hain and classi es the state space by iteratively applying reachability analysis. W e compare our method with the current state-of-the-art technique which requires the computation of the transitive closure of the transition relation of a Markov c hain. Experiments in over a dozen synchronous and asynchronous systems demonstrate that our method dramatically reduces the CPU time needed, and solves much larger problems because of reduced memory requiremen ts.
V. CONCLUSION We have presented a complete planar clock routing system called ACTD, which is implemented by employing heuristic techniques. Our first algorithm, called CLE routing, is implemented to solve the overlapping of clock net routing and prevent the crossing in the clock net. The second algorithm, called POA routing, reconstructs the clock tree using heuristics, to avoid obstacles with the scheme of changing tapping points. We have validated our techniques experimentally using test circuits. Future work includes extending the CLE routing and POA routing approach to include well-balanced clock trees, since our current implementation constructs a planar clock routing in the presence of obstacles with allowing the path length skew. Extending our present results to the minimum skew goal presents an intriguing direction for future work. We expect that partitioning line adjustment based on the weight of load and tapping point adjustment for a given planar clock tree will help to minimize clock skew.
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