This paper presents the new approach in implementation of analog-to-digital converter (ADC) that is based on Hopfield neural-network architecture. Hopfield neural ADC (NADC) is a type of recurrent neural network that is effective in solving simple optimization problems, such as analog-to-digital conversion. The main idea behind the proposed design is to use multiple 2-bit Hopfield NADCs operating as quantizers in parallel, where analog input signal to each successive 2-bit Hopfield ADC block is passed through a voltage level shifter. This is followed by a neural network encoder to remove the quantization errors. In traditional Hopfield NADC based designs, increasing the number of bits could require proper scaling of the network parameters, in particular digital output operating region. Furthermore, the resolution improvement of traditional Hopfield NADC creates digital error that increases with the increasing number of bits. The proposed design is scalable in number of bits and number of quantization levels, and can maintain the magnitude of digital output code within a manageable operating voltage range.

The emergence of optical Internet of Things (optical-IoT) for sixth-generation (6G) networks has been envisaged to relieve the bandwidth congestion in the conventional radio frequency (RF) channel, and to support the ever-increasing number of smart devices. Among the plethora of device innovations deemed essential for fortifying the development, herein we report on the visible-to-near-infrared colorconversion luminescent-dyes based on lead sulphide quantum dots (PbS QDs), so as to achieve an eyesafe high-speed optical link. The solution-processed PbS QDs exhibited strong absorption in the visible range, radiative recombination lifetime of 6.4 μs, as well as high photoluminescence quantum yield of up to 88%. Our proof-of-principle demonstration based on an orthogonal frequency-division multiplexing (OFDM) modulation scheme established an infrared data transmission of 0.27 Mbit/s, readily supporting an indoor optical-IoT system, and shed light on the possibility for PbS-integrated transceivers in supporting remote access control of multiple nodes. We further envisaged that our investigations could find applications in future development of solution-processable PbS-integrated luminescent fibers, concentrators, and waveguides for high-speed optical receivers.

In this chapter, we present an overview of the recent advances in analog-to-digital converter (ADC) neural networks. Biological neural networks consist of natural binarization reflected by the neurosynaptic processes. This natural analog-to-binary conversion ability of neurons can be modeled to emulate analog-to-digital conversion using a set of nonlinear circuit elements and existing artificial neural network models. Since one neuron during processing consumes on average only about half nanowatts of power, neurons can perform highly energy-efficient operations, including pattern recognition. Analog-to-digital conversion itself is an example of simple pattern recognition where input analog signal can be presented in one of the 2 N different patterns for N bits. The classical configuration of neural network-based ADC is Hopfield neural network ADC. Improved designs, such as modified Hopfield network ADC, T-model neural ADC, and multilevel neurons-based neural ADC, will be discussed. In addition, the latest architecture designs of neural ADC such as hybrid complementary metal-oxide semiconductor (CMOS)-memristor Hopfield ADC are covered at the end of this chapter.

Abstract-Increase in image resolution require the ability of image sensors to pack an increased number of circuit components in a given area. On the the other hand a high speed processing of signals from the sensors require the ability of pixel to carry out pixel parallel operations. In the paper, we propose a modified 3T and 4T CMOS wide dynamic range pixels, which we refer as 2T-M and 3T-M configurations, comprising of MOSFETS and memristors. The low leakage currents and low area of memristors helps to achieve the objective of reducing the area, while the possibility to create arrays of memristors and MOSFETs across different layers within the chip, ensure the possibility to scale the circuit architecture.

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