Matching water cuts of production wells is one of the most challenging tasks in the history matching process. When conducting history matching with a finite difference simulator, one of the challenges is how to define a suitable region for the permeability modifier to obtain a good match, and yet, retain major geological description. In the case of large models, the presence of several wells in a region where permability is adjusted makes simultaneous matching for these wells almost impossible. Commercial streamline simulators are best in reducing the mismatch in water cuts; however, it is cumbersome to include other uncertainty parameters such as water-oil contact, relative permeability, pressure-volume-temperature data, etc., during the optimization process. To combine the power of finite difference simulators and streamline technology, an in-house developed reservoir simulator was linked to a customized streamline tracing software package. This solution is capable of generating streamlines that represent a snapshot of the flow pattern within the reservoir, and providing well drainage region information and injector-producer relationships. This paper presents an automatic process in which the reservoir simulator is run via the control of a commercial optimizer, the simulation results are transferred to the streamline tracing package, which also tags the simulator cells to be modified by the optimizer without running a full streamline simulation. The optimizer then uses a global minimization method to fine-tune the permeability modifiers for reducing the water cut errors. This approach was verified by using two synthetic models in which the solution is known. Excellent results were obtained. Therefore, this approach makes it possible to employ the power and flexibility of finite difference simulators and optimization algorithms, with the crucial fluid flow information provided by streamline technology.
Superscalar architectures have been proposed that exploit control independence, reducing the performance penalty of branch mispredictions by preserving the work of future mispredictionindependent instructions. The essential goal of exploiting control independence is to completely decouple future mispredictionindependent instructions from deferred misprediction-dependent instructions. Current implementations fall short of this goal because they explicitly maintain program order among misprediction-independent and misprediction-dependent instructions. Explicit approaches sacrifice design efficiency and ultimately performance.We observe it is sufficient to emulate program order. Potential misprediction-dependent instructions are singled out a priori and their unchanging source values are checkpointed. These instructions and values are set aside as a "recovery program". Checkpointed source values break the data dependencies with comingled misprediction-independent instructions -now long since gone from the pipeline -achieving the essential decoupling objective. When the mispredicted branch resolves, recovery is achieved by fetching the self-sufficient, condensed recovery program. Recovery is effectively transparent to the pipeline, in that speculative state is not rolled back and recovery appears as a jump to code. A coarse-grain retirement substrate permits the relaxed order between the decoupled programs. Transparent control independence (TCI) yields a highly streamlined pipeline that quickly recycles resources based on conventional speculation, enabling a large window with small cycle-critical resources, and prevents many mispredictions from disrupting this large window.TCI achieves speedups as high as 64% (16% average) and 88% (22% average) for 4-issue and 8-issue pipelines, respectively, among 15 SPEC integer benchmarks. Factors that limit the performance of explicitly ordered approaches are quantified.
ZettaRAM™ is a new memory technology under development by ZettaCore™ as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor in each DRAM cell with "charge-storage" molecules -a molecular capacitor. We look beyond ZettaRAM's manufacturing benefits, and approach it from an architectural viewpoint to discover benefits within the domain of architectural metrics.The molecular capacitor is unusual because the amount of charge deposited (critical for reliable sensing) is independent of write voltage, i.e., there is a discrete threshold voltage above/below which the device is fully charged/discharged. Decoupling charge from voltage enables manipulation via arbitrarily small bitline swings, saving energy. However, while charge is voltageindependent, speed is voltage-dependent. Operating too close to the threshold causes molecules to overtake peripheral circuitry as the overall performance limiter. Nonetheless, ZettaRAM offers a novel speed/energy trade-off whereas DRAM is inflexible, introducing new dimensions for architectural management of memory.We apply architectural insights to tap the full extent of ZettaRAM's power savings without compromising performance. Several factors converge nicely to direct focus on L2 writebacks: (i) they account for 80% of row buffer misses in the main memory, thus most of the energy savings potential, and (ii) they do not directly stall the processor and thereby offer scheduling flexibility for tolerating extended molecule latency. Accordingly, slow writes (low energy) are applied to non-critical writebacks and fast writes (high energy) to critical fetches. The hybrid write policy is combined with two options for tolerating delayed writebacks: large buffers with access reordering or L2-cache eager writebacks. Eager writebacks are remarkably synergistic with ZettaRAM: initiating writebacks early in the L2 cache compensates for delaying them at the memory controller. Dual-speed writes coupled with eager writebacks yields energy savings of 34% (out of 41% with uniformly slow writes), with less than 1% performance degradation.
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