The cellular systems with 4th generation, Long Term Evolution (LTE) standard have been transmitted the data at higher rates than the 3G, and 2G systems, in an ever-crowded frequency spectrum. This transmission needs more accuracy, high reliability, and throughput with a low area and power consumption. Therefore, it requires an efficient error control coding. Turbo code is used for LTE system for its good error correction ability at low signal to noise power ratio which can approach Shannon limit performance for large frame lengths. This paper presents a simple and efficient modification that can be applied to all present stopping criterion (SC) to achieve the quality of service mentioned previously. It’s proved that using a trimmed sequence of log-likelihood values (LLR) instead of the full length in the algorithms of stopping the iterative decoding has a significant impact on the utilized silicon area and throughput without a significant sacrifice in performance. It also presents a comparison of designing the Soft-Output Viterbi (SOVA) decoder using different arbitrary-precision fixed data types that offers by Vivado high-level synthesis (HLS) instead of the costlier float representation to reduce processing time and consumed area. Due to its high flexibility in designing and implementing prototype systems, the FPGA device (Kintex-7, Xilinx part number XC7K325T-2FFG900C) was utilized with different parallelism and loop pipelining directives to ensure acquiring the targeted initiation interval and silicon area.
This study proposes a simple scaling factor approach to improve the performance of parallel-concatenated convolutional code (PCCC) and serial concatenated convolutional code (SCCC) systems based on suboptimal soft-input soft-output (SISO) decoders. Fixed and adaptive scaling factors were estimated to mitigate both the optimistic nature of a posteriori information and the correlation between intrinsic and extrinsic information produced by soft-output Viterbi (SOVA) decoders. The scaling factors could be computed off-line to reduce processing time and implementation complexity. The simulation results show a significant improvement in terms of bit-error rate (BER) over additive white Gaussian noise and Rayleigh fading channel. The convergence properties of the suggested iterative scheme are assessed using the extrinsic information transfer (EXIT) chart analysis technique.
This paper proposed an experimental device that emulates and facilitates teaching the theoretical concepts of error-control coding (ECC) techniques. Two prototypes laboratory boards were designed and implemented. The first board simulates the transmitter side of a typical digital communication system. It mainly contains a data source, (7,4) Hamming encoder, cyclic redundancy check encoder (CRC), and Gaussian noise generator. The second board has two types of Hamming decoders, a syndrome decoder, and a maximum likelihood (ML) decoder that accepts the received soft signals at the channel output. Each board has several control switches so that the trainee can change the code variables, noise power, user ID, in addition to display tools such as light-emitting diodes (LEDs), and test points for the oscilloscope that help the user to observe the results. Moreover, results and setting variables can also be displayed on a PC’s screen connected through a USB port and organic light emitting diodes (OLED) display that is attached to the receiver board. The pipelining architecture of the field programmable gate array (FPGA) device was exploited in this proposed system to reduce the processing delay and hence increase the data throughput. Furthermore, we proved that both theoretical and experimental tests are identical.
In this paper, an efficient early termination (ET) mechanism for systematic turbo-polar code (STPC) based on optimal estimation of scaling factor (SF) is proposed. The gradient of the regression line which best fits the distance between a priori and extrinsic information is used to estimate the SF. The multiplication of the extrinsic information by the proposed SF presents effectiveness in resolving the correlation issue between intrinsic and extrinsic reliability information traded between the two typical parallel concatenated soft-cancellation (SCAN) decoders. It is shown that the SF has improved the conventional STPC by about 0.3 dB with an interleaver length of 64 bits, and about 1 dB over the systematic polar code (SPC) at a bit error rate (BER) of . A new scheme is proposed as a stopping criterion, which is mainly based on the estimated value of SF at the second component decoder and the decoded frozen bits for each decoding iteration. It is shown that the proposed ET results in halving the average number of iterations (ANI) without adding considerable complexity. Moreover, the modified codes present comparable results in terms of BER to the codes that utilize fix number of iterations.
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