In this contribution, we report on the effect of pentacene thickness and temperature on the performance of top gate transistors. We first investigated the temperature dependence of the transport properties in the temperature range of 258 K -353 K. The electrical characteristics showed that the threshold voltage (V T ) and the onset voltage (V on ) remain unchanged. However, the subthreshold current (I off ), the on-current (I on ) and the field effect mobility (µ) are highly affected with a slight deterioration of subthreshold slope. We observed Arrhenius-like behavior suggesting a thermally activated mobility with an activation energy E A = 68 meV. Moreover the dependence of the charge carrier mobility on the organic semiconductor thickness has also been studied. The mobility decreased as the pentacene thickness increases whereas the threshold voltage and I off current remain minimally affected. In order to understand the transport properties and in view to put in light morphology peculiarities of pentacene, AFM images were performed. It turns out that the pentacene grain sizes are smaller and disorganized as the film thickness increases, and charge carriers are more prone to be trapped, leading to decrease the field effect mobility and the I on current. The devices were also tested under bias stress and the transistors with low thicknesses exhibited a relatively good electrical stability compared to those with high pentacene thicknesses. This work points out the influence of temperature, semiconductor thickness and bias stress effect on the device performance and stability of transistor using top gate configuration.
The idea to use ferroelectric materials (PZN-PT) came from the fact that the ferroelectric nature could facilitate electric charges accumulation on the interfaces of the solar cell. Thus, it would increase the open circuit voltage V oc which could reach more than 10 V. This would directly impact the efficiency which is proportional to V oc , thus hoping to obtain solar efficiency never equaled by the halide perovskites which are less stable and less resistant in aggressive environments. In this work, the solar cells produced gave an exceptional record efficiency of 39.32% with a very high open circuit voltage (V oc ) of 3.50 V, a short-circuit current density (J sc ) of 0.118 mA/cm 2 and an FF of 0.72 measured in the positive polarization direction under 3825 lux (5.6 W/m 2 ) lighting. The negative polarization direction under 4781 lux (7 W/m 2 ) lightning gave a current density of 2 mA/cm 2 , an open circuit voltage of 2.30 V and an FF of 0.35.
The present work relates to a process for silicon surface texturing for preparing large-area, silicon nanotextures on silicon substrates at ambient temperature by assisted chemical etching. A novel strategy comprises of two fundamental steps (metal-assisted chemical etching (MACE) and solution post-treatment) of using the silver catalyst to obtain specific nano-or micro-textures. The strategy is based on metal-induced (Ag) local oxidation and dissolution of a silicon substrate in three different concentrations of aqueous fluoride solution with the post-treatment solution. The etching technique is dependent on the etching time and concentration of aqueous fluoride solution. Therefore, detailed scanning electron microscopy observations reveal specifics shapes as inverted pyramids, cubic nano-microholes, spiroconical nano-microholes and rhombohedral-stared nanosheet bouquets (called Nanobukets), obtained for the first time on a (100) silicon surface by this new variant of the MACE method named Double Etching Method (DEM). Silicon nanostructures are used in many nanotechnology applications such as nano-microelectronics, optoelectronics or biomedical applications. UV-Visible spectrometry measurements carried out made it possible to obtain the lowest reflectance and highest absorbance values who are 3% and 97%, respectively for the rhomboedral-stared nanosheet bouquets on (100) crystalline silicon substrates in the UV-visible-NIR wavelength range from 300 to 1200 nm.
This study deals with electrical instability under bias stress in pentacene-based transistors with gate dielectrics deposited by a lamination process. Mylar film is laminated onto a polyethylene terephthalate (PET) substrate, on which aluminum (Al) gate is deposited, followed by evaporation of organic semiconductor and gold (Au) source/drain contacts in bottom gate top contact configuration (Device 1). In order to compare the influence of the semiconductor/dielectric interface, a second organic transistor (Device 2) which is different from the Device 1 by the deposition of an intermediate layer of polymethyl methacrylate (PMMA) onto the laminated Mylar dielectric and before evaporating pentacene layer is fabricated. The critical device parameters such as threshold voltage (VT), subthreshold slope (S), mobility (µ), onset voltage (Von) and Ion/Ioff ratio have been studied. The results showed that the recorded hysteresis depend on the pentacene morphology. Moreover, after bias stress application, the electrical parameters are highly modified for both devices according to the regimes in which the transistors are operating. In ON state regime, Device 1 showed a pronounced threshold voltage shift associated to charge trapping, while keeping the µ, Ioff current and S minimally affected. Regardless of whether Device 2 exhibited better electrical performances and stability in ON state, we observed a bias stress-induced increase of depletion current and subthreshold slope in subthreshold region, a sign of defect creation. Both devices showed onset voltage shift in opposite direction.
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