This paper investigates a fully-digital fixed frequency digital voltage-mode controller for DC-DC converters based on hysteresis modulation. The proposed architecture employes a digital-pulse width modulator (DPWM) and an analog-to-digital converter (ADC) based on a threshold inverter quantization (TIQ) technology, which enables flash-based analog-to-digital conversion and asynchronous detection of output voltage variations. One important property of the proposed solution is the high dynamic performance, since the control algorithm is based on the emulation of a hysteretic voltage mode control and on the asynchronous detection of the output voltage variations, which reduces control delay. An IC design of the TIQ-based ADC, tailored to DC-DC converters, and of a DPWM with time resolution down to 350 ps is also reported. Simulation and experimental results on a synchronous buck converter confirm the proposed analysis and the dynamic performances achievable by the proposed control architecture
The rapidly growing use of digital control in Distributed Power Architectures (DPA) has been primarily driven by the increasing need of sophisticated Power Management functions. However, specifically designed control algorithms can also be exploited for optimizing the system performance. In this paper we present a new auto-tuning method and system that makes it possible to operate an isolated DC-DC converter at maximum efficiency. The auto-tuning performs an optimum adjustment of both primary side dead time and secondary side conduction times based on the measurement of the input current. It does not require any additional external components since current sensing functions are already implemented for power management purposes. Experimental measurements performed on an asymmetrical driven half-bridge DC-DC converter demonstrate the effectiveness of our solution and its robustness to component variations.
This paper presents a new microstepping driving technique. The proposed approach exploits a digital current estimation algorithm and an integrator circuit to perform a 16 micro steps operation. The proposed solution allows, in an IC implementation, a consistent reduction of the silicon area compared to a conventional analog approach based on a 4 bit sinusoidal DAC. The presented control scheme was verified by experiments and an error analysis was performed
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