In this paper, a 4th-order low-pass continuous-time analog filter is presented, that is implemented with the cascade of two efficient and compact biquadratic cells, realized using the Super-Source-Follower topology. The biquadratic cell uses only two capacitors and four transistors: two transistors for the signal processing and two transistors as current sources for biasing purpose. The 4th-order filter prototype has been integrated in 0.18 µm CMOS technology. For a 33 MHz cut-off frequency, the filter performs 18 dBm-IIP3 for two tones at 2 MHz and 3 MHz, with total current of 770 µA from a single 1.8 V supply voltage.Index Terms-Analog filters, biquadratic cell, CMOS 0.18 m, continuous-time filters, low power, super source follower.

Abstract-This paper presents the simplified charge-based EKV MOSFET model and shows that it can be used for advanced CMOS processes despite its very few parameters. The concept of inversion coefficient IC is first introduced as an essential design parameter that replaces the overdrive voltage VG-VT 0 and spans the entire range of operating points from weak via moderate to strong inversion, including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40-nm and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation valid from weak to strong inversion and requiring only the VS parameter λc is described. The normalized transconductance efficiency Gm/ID, which is a key figure-of-merit (FoM) for the design of low-power analog circuit, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to strong inversion with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance G ds /ID follows a similar dependence with IC than the normalized Gm/ID characteristic but with different parameters accounting for DIBL. The methodology for extracting the few parameters from the measured ID-VG and ID-VD characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted SOI (FDSOI) and FinFET 28-nm processes.

This paper investigates the radiation tolerance of 28 nm bulk n-and pMOSFETs up to 1 Grad of total ionizing dose (TID). The radiation effects on this commercial 28 nm bulk CMOS process demonstrate a strong geometry dependence as a result of the complex interplay of oxide and interface charge trapping relevant to the gate-related dielectrics and the shallow trench isolation. The narrowest/longest-channel devices have the most serious performance degradation. In addition, nMOSFETs present a limited on-current variation and a significant offcurrent increase, while pMOSFETs show a negligible off-current change and a substantial on-current degradation. The postirradiation annealing annihilates or neutralizes oxide trapped positive charges and tends to partly recover the degraded device performance. To quantify the effects of TID and post-irradiation annealing, parameters including the threshold voltage, the free carrier mobility, the subthreshold swing, and the drain-induced barrier lowering are extracted.

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