Calibrating network analyzer is still an issue for bended access port devices (devices with access). Bended accesses can give additional errors which are taken into account by using a new design standards of Vector Network Analyzer (VNA) calibration. This Thru-Reflect-Line calibration technique is computed from ABCD parameters that easily allow to remove the bended port effects. This approach is based on the assumption that the Vector Network Analyzer error boxes can be considered as passive system. Furthermore, the method can be applied for de-embedding devices with bended accesses. This calibration and de-embedding technique could be applied, for example, to a coplanar circulator or a power divider measurement which have access lines at 120° from each other.
3D chip stacking is considered known to overcome conventional 2D-IC issues, using Trough Silicon Via (TSVs) to ensure vertical signal transmission between data. If the electrical behaviour of 3D interconnections (redistribution metal lines and through silicon vias) used in 3D IC stack technologies are to be explored in this paper, the substrate itself is of interest, via Green Kernels by solving Poisson's equation analytically. Using this technique, the substrate coupling and loss in IC's can be analysed. We implement our algorithms in MATLAB. This method has been already used; but, it permits to extract impedances for a stacked uniform layers substrate. We have extended for any numbers of embedded contacts, of any shape. On a second hand, we grasp the background noise between any two points, in the bulk, or at the surface, from a transfer impedance extraction technique. With an analog algorithm, a strength of this work, we calculate unsteady solutions of the heat equation, using a spreading resistance concept. This method has been adapted to stacked layers. With this general tool of impedance field, we investigate on the problems encountered by interconnects, especially the vias, the substrate, and their entanglement. A calculation of thermal mechanical stresses and their effects on substrate crack (max and min stresses), devices (i.e: transistors) and hotspots, are made to track the performance. But, to well understand the interconnection incidence on 3D system performances, it is important to consider the whole electrical context; it seems relevant to consider the possible couplings between vias, not only by the electromagnetic field, but also by any possible energy transfer between interconnects; more generally, one of actual problem is to determine where the energy is really confined in such 3D circuits, before find solutions to limit pollutions coming from electro-magneto -thermal phenomena or background noises.
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