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GaN growth on heterosubstrates usually leads to an initially high dislocation density at the substrate/seed layer interface. Due to the initial growth from small crystallites, tensile stress is generated at the coalescence boundaries during GaN growth. In addition, with tensile thermal stress this leads to cracking of GaN on Si and SiC substrates when cooling to room temperature. By partially masking the typically applied AlN seed layer on Si(111) with an in situ deposited SiN mask a reduction in tensile stress can be achieved for the subsequently grown GaN layer. Additionally, the 6 K GaN band edge photoluminescence is increased by about an order of magnitude and shifts by 21 meV, which can be attributed to a change in tensile stress of ∼0.8 GPa, in good agreement with x-ray diffractometry measurements. This improvement in material properties can be attributed to a reduction of grain boundaries by the growth of larger sized crystallites and lateral overgrowth of less defective GaN.

GaN growth on Si is very attractive for low-cost optoelectronics and high-frequency, high-power electronics. It also opens a route towards an integration with Si electronics. Early attempts to grow GaN on Si suffered from large lattice and thermal mismatch and the strong chemical reactivity of Ga and Si at elevated temperatures. The latter problem can be easily solved using gallium-free seed layers as nitrided AlAs and AlN. The key problem for device structure growth on Si is the thermal mismatch leading to cracks for layer thicknesses above 1 µm. Meanwhile, several concepts for strain engineering exist as patterning, Al(Ga)N/GaN superlattices, and low-temperature (LT) AlN interlayers which enable the growth of device-relevant GaN thicknesses. The high dislocation density in the heteropitaxial films can be reduced by several methods which are based on lateral epitaxial overgrowth using ex-situ masking or patterning and by in-situ methods as masking with monolayer thick SiN. With the latter method in combination with strain engineering by LT-AlN interlayers dislocation densities around 109 cm -2 can be achieved for 2.5 µm thick device structures.

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