Operational transconductance amplifiers are high gain amplifiers with wide bandwidth. The main advantage of those circuits is their capability to drive high resistive and capacitive loads at their outputs. Due to such capability, such circuits consume high power. While in some applications where the current consumption may vary in wide ranges the self-current of those amplifiers may succeed the load current, thus decreasing the efficiency coefficient of the designs. To reduce the intrinsic current consumption without impacting the performance and functionality, a novel method of an operational transconductance amplifier output stage design is proposed in this paper. The programmable output stage, in which the output cascade can operate in two different modes using a digital control signal has been designed. As a result, the parameters of the operational amplifier become more flexible to be tuned and configured after production. The output impedance, amplifier transconductance, bandwidth and other main parameters can be easily controlled based on the system state. If the load at the output enters the power down mode, the impedance of the amplifiers decreases the current and vice versa. The solution has been tested in the modern 14nm FinFet technology and the achieved results have ensured the capability of the proposed solution to be integrated with modern analog integrated circuits.
In modern integrated circuits the number of devices have strongly increased. As a result, identifying the issues which have an impact on their performance stands out as a very complicated and challenging problem. In digital integrated circuits there are methods which are known, as well as some others which are in the active development stages targeted to enable the built-in self-tests, identify, and report those issues. At that, for mixed signal circuits, where the calculations or functions are performed based on the voltage levels, it is much complicated to develop self-testing mechanisms. A novel method of identifying the lack of clock signal and its duty cycle variation is proposed in this paper. The developed architectures and solutions are capable of detecting the lack of the clock signals, as well as informing the digital parts of the systems about the requirement for the coarse or fine tunings of the clock generation systems outside their autocalibration and loops.
The design of a software tool for calculating decoupling capacitors in integrated circuits has been proposed, which allows the user to make accurate schematic calculations of the solutions used in those circuits without programming knowledge through simple inputs. PowerIC Decap Calculator allows the user to calculate the required capacity of decoupling capacitors, allowing it to be placed on the free surface of the integrated circuit (IC) entered by the designer. The capacity calculation is performed taking into account the existing and proposed methods of design of decongesting capacitors, which in turn increases the flexibility of the proposed solution. The introduction of the PowerIC Decap Calculator in the design process of ICs allows, in the early stages of the design when the physical design of the IC has not been completed, to perform the calculations of decoupling capacitors’ capacities based on the values of the limitations in the current area. As a result of calculation, in the case of designing decoupling capacitors with the joint use of MOM and capacitors with MOS structures, the area occupied by these elements in IC is reduced by 1.5 times, at the same time, the dependence of these elements on the deviation of technological processes is reduced. The calculation takes about 4 minutes.
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