Fluctuations in manufactured integrated circuit parameters may dramatically reduce the parametric yield. Yield maximization can be formulated as an unconstrained optimization problem in nominal parameter values, which is known as design centering. The high expense of yield evaluations, the absence of any gradient information, and the presence of some numerical noise obstruct the use of the traditional derivative-based optimization methods. In this article, a novel design centering algorithm is presented, which consists of a non-derivative unconstrained optimizer coupled with a variance reduction estimator. The used optimizer combines a trust region mechanism with quadratic interpolation and provides efficient use of yield evaluations. The stratified sampling technique is used to develop a lower variance yield estimator that reduces the number of circuit simulations required to reach a desired accuracy level. Numerical and practical circuit examples are used to demonstrate the efficiency of the proposed algorithm with respect to other methods in the same field.

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A new technique for constructing a polyhedral approximation of the feasible region and finding the associated design center through a parallel-cuts ellipsoidal technique is presented. The linearizations of the feasible region boundary required to implement the parallel-cuts ellipsoidal technique are saved from one iteration to another in a non-redundant form. These linearizations are used in the construction of the parallel cuts as well as in the generation of an exterior polyhedral approximation of the feasible region at no additional cost. Numerical and practical examples are given to demonstrate the effectiveness of the new technique.

Fluctuations in manufactured circuit parameters may dramatically reduce the parametric yield. Yield maximization can be formulated as an unconstrained optimization problem. The high expense of yield evaluations, the absence of any gradient information, and the presence of some numerical noise obstruct the traditional derivative-based optimizers. In this paper we present a yield maximization algorithm that consists of a nonderivative unconstrained optimizer coupled with a variance reduction technique. The used optimizer combines trust region mechanism with quadratic interpolation and requires few yield evaluations. The stratified sampling technique is used to develop a lower variance yield estimator that, reduces the number of circuit simulations required to reach a desired accuracy level. Numerical and practical circuit examples are used to investigate the proposed algorithm.