π-SoC: Heterogeneous SoC Architecture for Visual Inertial SLAM Applications

Tang, Jie; Bo, Yu; Liu, Shaoshan; Zhang, Zhe; Fang, Weikang; Zhang, Yanjun

doi:10.1109/iros.2018.8594181

Cited by 21 publications

(11 citation statements)

References 7 publications

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“…In the next step, we plan to extend LoPECS to support more heterogeneous edge computing architectures with more diverse computing hardware, including DSP, FPGA, and ASIC accelerators [32]- [34]. Besides low-speed autonomous driving, we believe LoPECS has much broader applications: by porting LoPECS to more powerful heterogeneous edge computing systems, we can deliver the computing power to L3/L4 autonomous driving; and with more affordable edge computing systems, LoPECS can be applied for delivery robots, industrial robots, etc.…”

Section: Discussionmentioning

confidence: 99%

“…Task scheduling in heterogeneous environments has been proven to be a NP-complete problem and no absolute optimum exists. In [34], authors made a comparison of 11 independent task scheduling heuristics, including Min-Min [29], Max-Min [39], Genetic Algorithm (GA) [40]. The results show that Min-Min has the best comprehensive performance.…”

Section: B Inter-core Schedulermentioning

confidence: 99%

See 1 more Smart Citation

LoPECS: A Low-Power Edge Computing System for Real-Time Autonomous Driving Services

Tang

Liu²,

Liu

et al. 2020

IEEE Access

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To simultaneously enable multiple autonomous driving services on affordable embedded systems, we designed and implemented LoPECS, a Low-Power Edge Computing System for real-time autonomous robots and vehicles services. The contributions of this paper are threefold: first, we developed a Heterogeneity-Aware Runtime Layer to fully utilize vehicle's heterogeneous computing resources to fulfill the real-time requirement of autonomous driving applications; second, we developed a vehicle-edge Coordinator to dynamically offload vehicle tasks to edge cloudlet to further optimize user experience in the way of prolonged battery life; third, we successfully integrated these components into LoPECS system and implemented it on Nvidia Jetson TX1. To the best of our knowledge, this is the first complete edge computing system in a production autonomous vehicle. Our implementation on Nvidia Jetson demonstrated that it could successfully support multiple autonomous driving services with only 11 W of power consumption, and hence proves the effectiveness of the proposed LoPECS system. INDEX TERMS Edge computing, QoE (quality of experience), low power, autonomous driving.

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Section: Discussionmentioning

confidence: 99%

Section: B Inter-core Schedulermentioning

confidence: 99%

LoPECS: A Low-Power Edge Computing System for Real-Time Autonomous Driving Services

Tang

Liu²,

Liu

et al. 2020

IEEE Access

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“…Jie Tang et al (2020) proposed the low-cost real-time autonomous vehicle (Dragonfly Pod) with three modules, such as LoPECS (Low-Power Edge Computing System) and CNN for real-time object detection and speech recognition module with the heterogeneous multicore platform at an affordable price of $10,000 [28]. Recently many autonomous vehicles are connected with mobile edge computing servers, and mobile devices are used to monitor and control the services in real-time.…”

Section: Smruti Et Al (2019) Focused Onmentioning

confidence: 99%

An Intelligent Task Scheduling Mechanism for Autonomous Vehicles via Deep Learning

2021

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With the rapid development of the Internet of Things (IoT) and artificial intelligence, autonomous vehicles have received much attention in recent years. Safe driving is one of the essential concerns of self-driving cars. The main problem in providing better safe driving requires an efficient inference system for real-time task management and autonomous control. Due to limited battery life and computing power, reducing execution time and resource consumption can be a daunting process. This paper addressed these challenges and developed an intelligent task management system for IoT-based autonomous vehicles. For each task processing, a supervised resource predictor is invoked for optimal hardware cluster selection. Tasks are executed based on the earliest hyper period first (EHF) scheduler to achieve optimal task error rate and schedule length performance. The single-layer feedforward neural network (SLFN) and lightweight learning approaches are designed to distribute each task to the appropriate processor based on their emergency and CPU utilization. We developed this intelligent task management module in python and experimentally tested it on multicore SoCs (Odroid Xu4 and NVIDIA Jetson embedded platforms).Connected Autonomous Vehicles (CAV) and Internet of Medical Things (IoMT) benchmarks are used for training and testing purposes. The proposed modules are validated by observing the task miss rate, resource utilization, and energy consumption metrics compared with state-of-art heuristics. SLFN-EHF task scheduler achieved better results in an average of 98% accuracy, and in an average of 20–27% reduced in execution time and 32–45% in task miss rate metric than conventional methods.

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“…The FPGA was used for computationally intensive tasks, however, it implied restricting the memory dedicated to the algorithm and, therefore, limiting the data extracted from the video feed. A successful implementation is discussed in [20], where the π-SoC architecture is proposed. The architecture optimizes the input-output interface, the memory hierarchy, and the hardware accelerator, being able to optimize performance and power consumption in visual SLAM applications and not only speed up some algorithm processes.…”

Section: Related Workmentioning

confidence: 99%

Embbedded System-on-Chip 3D Localization and Mapping—eSoC-SLAM

Gerlein

Díaz-Guevara

Carrillo³

et al. 2021

Electronics

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This paper discusses a novel embedded system-on-chip 3D localization and mapping (eSoC-LAM) implementation, that followed a co-design approach with the primary aim of being deployed in a small system on a programmable chip (SoPC), the Intel’s (a.k.a Altera) Cyclone V 5CSEMA5F31C6N, available in the Terasic’s board DE1-SoC. This computer board incorporates an 800 MHz Dual-core ARM Cortex-A9 and a Cyclone V FPGA with 85k programmable logic elements and 4450 Kbits of embedded memory running at 50 MHz. We report experiments of the eSoC-LAM implementation using a Robosense’s 3D LiDAR RS-16 sensor in a Robotis’ TurtleBot2 differential robot, both controlled by a Terasic’s board DE1-SoC. This paper presents a comprehensive description of the designed architecture, design constraints, resource optimization, HPS-FPGA exchange of information, and co-design results. The eSoC-LAM implementation reached an average speed-up of 6.5× when compared with a version of the algorithm running in a the hard processor system of the Cyclone V device, and a performance of nearly 32 fps, while keeping high map accuracy.

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π-SoC: Heterogeneous SoC Architecture for Visual Inertial SLAM Applications

Cited by 21 publications

References 7 publications

LoPECS: A Low-Power Edge Computing System for Real-Time Autonomous Driving Services

LoPECS: A Low-Power Edge Computing System for Real-Time Autonomous Driving Services

An Intelligent Task Scheduling Mechanism for Autonomous Vehicles via Deep Learning

Embbedded System-on-Chip 3D Localization and Mapping—eSoC-SLAM

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