Ανάπτυξη Τεχνολογίας Κατασκευής Τρανζίστορς Λεπτών Υμενίων Βελτιστοποιημένων Ως Προς Τη Δομή Των Υμενίων Πυριτίου Που Προκύπτει Από Την Κρυσταλλοποίηση

Abstract

Low temperature polycrystalline silicon thin film transistors (LTPS TFTs) are essential for large area electronics and high performance flat panel displays. In recent years, LTPS TFT performance has substantially increased due to the important breakthroughs in the field of polycrystalline silicon crystallization and also due to the optimization of the process steps that differ from those of typical MOSFETs, mainly because of the requirement for low temperature procedures. The object of the present dissertation was the electrical characterization of polycrystalline Silicon thin film transistors (poly-Si TFTs), crystallized with different variations of the advanced technique SLS ELA, and the determination of process technological parameters that affect the device performance, in order to further optimize the production of such high performance transistors. We began studying the effect of the TFT active region film microstructure, relating the film characteristics themselves with the electrical performance of the TFTs. Then, we examined the relationship between critical process steps-namely gate dielectric deposition, doping and activation and the channel dimensions to be selected-and TFT electrical characteristics. We also studied the role of the topology (top gate, bottom gate, double gate) on TFT performance. Finally, attempting to further optimize the fabrication process of LTPS TFTs, we tried to modify the typical procedure, studying the use of alternative gate dielectrics.