Zero‐quantised discrete cosine transform coefficients prediction technique for intra‐frame video encoding

Jridi, Maher; Meher, Pramod Kumar; Alfalou, Ayman

doi:10.1049/iet-ipr.2012.0145

Cited by 2 publications

(1 citation statement)

References 12 publications

(55 reference statements)

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“…Thus, Config4 allowed a power efficiency about 7.7 times better than what we could obtain with Config1. We finally should note that hardware performance may be enhanced when using predictive computation techniques as in [33] to predict zero quantized DCT coefficients, or also by a fine hardware optimization of arithmetic operations used in the DCT, as in [34].…”

Section: Resource Utilizationmentioning

confidence: 99%

SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform

Jridi

Chapel

Dorez

et al. 2018

JLPEA

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This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due to cloud latency and privacy concerns. With edge computing, data are processed, analyzed, and encrypted very close to the device, which enable the ability to secure data and act rapidly on connected things. The proposed edge computing system is composed of a reconfigurable module to simultaneously compress and encrypt multiple images, along with wireless image transmission and display functionalities. A lightweight implementation of the proposed design is obtained by approximate computing of the discrete cosine transform (DCT) and by using a simple chaotic generator which greatly enhances the encryption efficiency. The deployed solution includes four configurations based on HW/SW partitioning in order to handle the compromise between execution time, area, and energy consumption. It was found with the experimental setup that by moving more components to hardware execution, a timing speedup of more than nine times could be achieved with a negligible amount of energy consumption. The power efficiency was then enhanced by a ratio of 7.7 times.

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Section: Resource Utilizationmentioning

confidence: 99%

SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform

Jridi

Chapel

Dorez

et al. 2018

JLPEA

Self Cite

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A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT

Jridi

Alfalou

Meher

2015

IEEE Trans. Circuits Syst. I

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International audienceApproximation of discrete cosine transform (DCT) is useful for reducing its computational complexity without significant impact on its coding performance. Most of the existing algorithms for approximation of the DCT target only the DCT of small transform lengths, and some of them are non-orthogonal. This paper presents a generalized recursive algorithm to obtain orthogonal approximation of DCT where an approximate DCT of length N could be derived from a pair of DCTs of length (N/2) at the cost of N additions for input preprocessing. We perform recursive sparse matrix decomposition and make use of the symmetries of DCT basis vectors for deriving the proposed approximation algorithm. Proposed algorithm is highly scalable for hardware as well as software implementation of DCT of higher lengths, and it can make use of the existing approximation of 8-point DCT to obtain approximate DCT of any power of two length, N > 8. We demonstrate that the proposed approximation of DCT provides comparable or better image and video compression performance than the existing approximation methods. It is shown that proposed algorithm involves lower arithmetic complexity compared with the other existing approximation algorithms. We have presented a fully scalable reconfigurable parallel architecture for the computation of approximate DCT based on the proposed algorithm. One uniquely interesting feature of the proposed design is that it could be configured for the computation of a 32-point DCT or for parallel computation of two 16-point DCTs or four 8-point DCTs with a marginal control overhead. The proposed architecture is found to offer many advantages in terms of hardware complexity, regularity and modularity. Experimental results obtained from FPGA implementation show the advantage of the proposed method

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Zero‐quantised discrete cosine transform coefficients prediction technique for intra‐frame video encoding

Cited by 2 publications

References 12 publications

SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform

SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform

A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT

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