Zen3: The AMD 2<sup>nd</sup>-Generation 7nm x86-64 Microprocessor Core

Burd, Thomas D.; Li, Wilson; Pistole, James; Venkataraman, Srividhya; McCabe, Michael T.; Johnson, Timothy J.; Vinh, James; Yiu, Thomas; Wasio, Mark; Wong, Hon-Hin; Lieu, Daryl; White, Jonathan M.; Munger, Benjamin; Lindner, Joshua; Olson, J.; Bakke, Steven; Sniderman, Jeshuah; Henrion, Carson; Schreiber, Russell; Busta, Eric; Johnson, Brett C.; Jackson, Tim; Miller, Aron; Miller, Ryan S.; Pickett, Matthew D.; Horiuchi, Aaron; Dvořák, Josef; Balagangadharan, Sabeesh; Ammikkallingal, Sajeesh; Kumar, Pankaj

doi:10.1109/isscc42614.2022.9731678

Cited by 19 publications

(3 citation statements)

References 4 publications

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“…When it comes down to multi-core application, per-core individual power supply has been proven to be an energy saving system approach [48], [49]. Prior multiple-output designs mainly focused on how to effectively reuse a single power inductor for multiple outputs [50]- [52].…”

Section: F Multiple-output Hybrid Buckmentioning

confidence: 99%

An Overview of Hybrid DC–DC Converters: From Seeds to Leaves

Lu,

Huang,

Tong

et al. 2024

IEEE Open J. Solid-State Circuits Soc.

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With the surging demands for higher current at sub-1V supply level in high performance digital systems, high-efficiency and high-current-density power converters are essential for system integration. Higher voltage supply buses are emerging for high current applications to reduce the IR losses on the power delivery networks. Thus, there is a wide voltage gap between the power bus and the digital supply rails at the point-of-load (PoL). Meanwhile, battery-powered portable or wearable devices favor extremely high-power-density solutions, calling for novel power conversion topologies, which has been the hottest topic in the power management IC area in the past decade. This paper reviews the switched-capacitor-inductor (SCI) hybrid DC-DC buck converters from the topology "seeds" to their "leaves". Here, we define six seeds, they are: 1) three-level buck, 2) double-step down buck, 3) inductor-first buck, 4) always-dual-path buck, 5) buck-buck, 6) multiple-output hybrid buck. We try to analyze and summarize their pros and cons, and to derive the evolution of the hybrid DC-DC converters, with milestone examples. Then, we share our observations, design intuitions and suggestions to help the researchers and engineers to pick up and design a new SCI hybrid DC-DC converter.

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Section: F Multiple-output Hybrid Buckmentioning

confidence: 99%

An Overview of Hybrid DC–DC Converters: From Seeds to Leaves

Lu,

Huang,

Tong

et al. 2024

IEEE Open J. Solid-State Circuits Soc.

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“…Each core has private L1 and L2 caches, and the L3 cache (also called LLC interchangeably) is shared among all cores/threads running in the system. This is representative of recent designs from major CPU manufacturers [13], [24], [35], [38], [61]. While L1 and L2 caches can be shared by threads simultaneously running on the same core in a simultaneously multithreaded (SMT) processor, we do not consider SMT in this paper -it is often disabled for security.…”

Section: A Cache Hierarchiesmentioning

confidence: 99%

TEE-SHirT: Scalable Leakage-Free Cache Hierarchies for TEEs

Arikan,

Farrell,

Cen

et al. 2024

Proceedings 2024 Network and Distributed System Security Symposium

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Protection of cache hierarchies from side-channel attacks is critical for building secure systems, particularly the ones using Trusted Execution Environments (TEEs). In this paper, we consider the problem of efficient and secure fine-grained partitioning of cache hierarchies and propose a framework, called Secure Hierarchies for TEEs (TEE-SHirT). In the context of a three-level cache system, TEE-SHirT consists of partitioned shared last-level cache, partitioned private L2 caches, and nonpartitioned L1 caches that are flushed on context switches and system calls. Efficient and correct partitioning requires careful design. Towards this goal, TEE-SHirT makes three contributions: 1) we demonstrate how the hardware structures used for holding cache partitioning metadata can be effectively virtualized to avoid flushing of cache partition content on context switches and system calls; 2) we show how to support multi-threaded enclaves in TEE-SHirT, addressing the issues of coherency and consistency that arise with both intra-core and inter-core data sharing; 3) we develop a formal security model for TEE-SHirT to rigorously reason about the security of our design.

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“…Heterogeneous CPU-GPU systems in which CPU and GPU cores are integrated on the same chip have become a popular trend recently, for example, Intel Alder Lake [1], Nvidia Orin [2], and AMD Cezanne [3]. The physical integration enables the CPU and GPU cores to share memory resources such as the last-level cache (LLC) and the main memory.…”

Section: Introductionmentioning

confidence: 99%

Reuse distance-based shared LLC management mechanism for heterogeneous CPU-GPU systems

Liu,

Egawa,

Takahashi

et al. 2024

IEICE Electron. Express

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Heterogeneous systems with CPU and GPU cores integrated on a single chip provide fast communication between CPU and GPU cores and high performance. The last-level cache (LLC) is one of the most essential shared memory resources in heterogeneous CPU-GPU systems. Due to the different LLC access behaviors and collaboration patterns from CPU and GPU, the shared LLC is not guaranteed to be used efficiently without any management. In this paper, we propose a reuse distance-based LLC management mechanism to improve system performance and save energy consumption. Our mechanism monitors reuse distances of cache lines accessed by CPU and GPU in sampling cache sets. It compares average reuse distance values of CPU and GPU cores to determine cache line insertion, promotion, and eviction in the LLC. Our mechanism can achieve significant performance improvement with a higher LLC hit rate. The evaluation results show that our management method can improve performance by up to 16% and 7%, and achieve LLC energy savings of up to 13% and 4% over the LRU and TAP-RRIP policies, respectively.

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Zen3: The AMD 2^nd-Generation 7nm x86-64 Microprocessor Core

Cited by 19 publications

References 4 publications

An Overview of Hybrid DC–DC Converters: From Seeds to Leaves

An Overview of Hybrid DC–DC Converters: From Seeds to Leaves

TEE-SHirT: Scalable Leakage-Free Cache Hierarchies for TEEs

Reuse distance-based shared LLC management mechanism for heterogeneous CPU-GPU systems

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Zen3: The AMD 2nd-Generation 7nm x86-64 Microprocessor Core

Cited by 19 publications

References 4 publications

An Overview of Hybrid DC–DC Converters: From Seeds to Leaves

An Overview of Hybrid DC–DC Converters: From Seeds to Leaves

TEE-SHirT: Scalable Leakage-Free Cache Hierarchies for TEEs

Reuse distance-based shared LLC management mechanism for heterogeneous CPU-GPU systems

Contact Info

Product

Resources

About

Zen3: The AMD 2^nd-Generation 7nm x86-64 Microprocessor Core