z/CECSIM: An efficient and comprehensive microcode simulator for the IBM eServer z900

Abstract

An IBM eServer zSeries TM system uses various types of microcode (firmware) that implement functions such as the execution of complex instructions in the CPUs, I/O operations performed by the system assist processors (SAPs), the management of logical partitions (LPARs), and control by the support element (SE). Each microcode component must be verified by itself and in conjunction with the others. Tight development schedules and a very limited supply of expensive engineering hardware make it desirable to perform this verification in a simulation environment. For the development of the z900, a new microcode simulator, the z/CECSIM (Central Electronic Complex Simulator), was successfully implemented. Several microcode components are connected in a single simulation environment, thereby allowing an unprecedented amount of development, integration, and testing without the use of engineering hardware. z/CECSIM creates a virtual zSeries CEC on VM/ESA ® or z/VM TM that allows the simulation of zSeries microcode. It executes the instruction stream as completely as possible on the underlying hardware. Only instructions that are newly introduced with the system being developed or that perform a microcode-internal function are simulated. Additional software models mimic the behavior of I/O and coupling channels. An optional SE connection allows verification of interactions between the CEC and its support element.

Reliability, availability, and serviceability (RAS) of the IBM eServer z990

“…For example, a complete multibook IML, including LPAR partition activation, was achieved using the central electronic complex simulation (z/CECSIM) microcode simulator as described in [3], enhanced for the z990 server. Reaching this target using the actual LIC from all subsystems was an important milestone in reducing test effort.…”

The GNU 64-bit PL8 compiler: Toward an open standard environment for firmware development

“…The validation effort used the usual set of tools required for zSeries firmware code generation [5,13]. The major (and fundamentally new) part is the GPL8 front end to the GCC compiler, but it also covers the whole tool chain (i.e., assembler and linker) needed for processing PL8.…”

“…The major (and fundamentally new) part is the GPL8 front end to the GCC compiler, but it also covers the whole tool chain (i.e., assembler and linker) needed for processing PL8. A key element for testing was a special VM/CMS-based simulation and debugging environment called z/CECSIM [13]. For normal code development and test purposes, about 1300 functional test cases are available.…”

Hyper-acceleration and HW/SW co-verification as an essential part of IBM eServer z900 verification

“…Speed of this magnitude is needed for efficient debugging of IML code. To address this problem, the construction of one of the largest hyper-acceleration systems ever created has been initiated; this is the CoBALT TM system, 1 which is installed at IBM Boeblingen. The system was developed under a partnership with the Quickturn Corporation.…”

“…By applying these methods first to units, then to single chips, and finally to multiple chips, almost all hardware problems can be found prior to "tape-out" by using standard simulation techniques. The majority of the code is typically verified without the target hardware [1] by using behavioral models. This is sufficient as long as the code does not access special-purpose hardware features, which are usually not added to the behavioral models because of their complexity.…”