YOLOv2-tiny Target Detection System Based on FPGA Platform

Zhou, Hangjian; Xiao, Yingxu; Zheng, Zhizhong; Yang, Bin

doi:10.1109/icbaie56435.2022.9985817

“…To minimize computational costs and simplify the model, reducing the size of these feature maps is necessary. The max-pooling technique is employed to achieve this while preserving spatial invariance of distinct features within the feature maps [8,9]. Typically, a window of size 2 × 2 is used in max-pooling operations, ensuring spatial overlap of the maximum values and sampling values along the horizontal and vertical axes every two positions [9].…”

Section: Introductionmentioning

confidence: 99%

“…The max-pooling technique is employed to achieve this while preserving spatial invariance of distinct features within the feature maps [8,9]. Typically, a window of size 2 × 2 is used in max-pooling operations, ensuring spatial overlap of the maximum values and sampling values along the horizontal and vertical axes every two positions [9]. As a result, the feature map's width and height can be reduced by half, resulting in a 4× reduction in size while preserving the maximum values that represent the distinct features of the feature map.…”

Section: Introductionmentioning

confidence: 99%

Efficient Two-Stage Max-Pooling Engines for an FPGA-Based Convolutional Neural Network

Hong,

Choi,

Joo

2023

Electronics

2

0

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This paper proposes two max-pooling engines, named the RTB-MAXP engine and the CMB-MAXP engine, with a scalable window size parameter for FPGA-based convolutional neural network (CNN) implementation. The max-pooling operation for the CNN can be decomposed into two stages, i.e., a horizontal axis max-pooling operation and a vertical axis max-pooling operation. These two one-dimensional max-pooling operations are performed by tracking the rank of the values within the window in the RTB-MAXP engine and cascading the maximum operations of the values in the CMB-MAXP engine. Both the RTB-MAXP engine and the CMB-MAXP engine were implemented using VHSIC hardware description language (VHDL) and verified by simulations. The implementation results demonstrate that the 16 CMB-MAXP engines achieved a remarkable throughput of about 9 GBPS (gigabytes per second) while utilizing only about 3% of the available resources on the Xilinx Virtex UltraScale+ FPGA XCVU9P. On the other hand, the 16 RTB-MAXP engines exhibited somewhat lower throughput and resource utilization, although they did offer a slightly better latency when compared to the CMB-MAXP engines. In the comparison with existing techniques, the CMB-MAXP engine exhibited comparable implementation results in terms of the resource utilization and maximum operating frequency. It is crucial to note that only the proposed engines provide the features of runtime window scalability and boundary padding capability, which are essential requirements for CNN accelerators. The proposed max-pooling engines were employed and tested in our CNN accelerator targeting the CNN model YOLOv4-CSP-S-Leaky for object detection.

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Research on Image Recognition of Tuberculosis Lesions by Minimally Invasive Surgical Robot Based on YOLOv2

朱

2024

AIRR

0

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Efficient Two-Stage Max-Pooling Engines for an FPGA-based Convolutional Neural Network

Hong,

Choi,

Joo

2023

Preprint

0

View full text Add to dashboard Cite

This paper proposes two max-pooling engines, named the RTB-MAXP engine and the CMB-MAXP engine, with a scalable window size parameter for FPGA-based convolutional neural network (CNN) implementation. The max-pooling operation for the CNN can be decomposed into two stages, i.e., a horizontal axis max-pooling operation and a vertical axis max-pooling operation. These two one-dimensional max-pooling operations are performed by tracking the rank of the values within the window in the RTB-MAXP engine and cascading the maximum operations of the values in CMB-MAXP engine. Both the RBM-MAXP engine and the CMB-MAXP engine were implemented using VHSIC Hardware Description Language (VHDL) and verified by simulations. They have been employed for and tested in our CNN accelerator targeting at the CNN model YOLOv4-CSP-S-Leaky for object detection.

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YOLOv2-tiny Target Detection System Based on FPGA Platform

Cited by 3 publications

References 11 publications

Efficient Two-Stage Max-Pooling Engines for an FPGA-Based Convolutional Neural Network

Efficient Two-Stage Max-Pooling Engines for an FPGA-Based Convolutional Neural Network

Research on Image Recognition of Tuberculosis Lesions by Minimally Invasive Surgical Robot Based on YOLOv2

Efficient Two-Stage Max-Pooling Engines for an FPGA-based Convolutional Neural Network

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