Yield increase of VLSI after redundancy-repairing

Hirase, J.

doi:10.1109/ats.2001.990308

Cited by 16 publications

(14 citation statements)

References 4 publications

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“…Redundancy repair techniques are widely employed in modern DRAM systems to recover from various faults and to prevent system failures [1,2,3,4]. Such repair techniques are designed to substitute spare elements for faulty elements, particularly permanent faults due to manufacturing defects.…”

Section: Introductionmentioning

confidence: 99%

A decoupled bit shifting technique using data encoding/decoding for DRAM redundancy repair

Choi

Jun

Kim

et al. 2017

IEICE Electron. Express

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Redundancy repairs are commonly used to support fault tolerance in DRAM systems and recently, the processor performance has been greatly improved, so DRAM access latency has become an important issue. However, existing redundancy repairs using shift logic have difficulty in further reducing the latency due to their design limitations. In this paper, we propose a novel, decoupled bit shifting technique that uses data encoding and decoding to resolve this limitation. Our technique decouples the conventional shifting logic into two units, a bit selection vector generator (BSVG) and a data manipulation unit (DMU), to reduce the latency overhead of the shifting logic. Our technique can apply the BSVG in parallel with other logic consuming long latency operations, thereby reducing the total latency compared to conventional shifting logic. We implement both serial and parallel approaches to demonstrate that the parallel approach performs significantly better than the serial one in terms of delay, area, and dynamic power consumption. The experimental results show that our bit shifting technique is applicable for redundancy repair technique in state-of-the-art DRAM architectures.

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Section: Introductionmentioning

confidence: 99%

A decoupled bit shifting technique using data encoding/decoding for DRAM redundancy repair

Choi

Jun

Kim

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Yield model for VLSI redundancy repair has been well developed [13] [14]. However, yield model for MEMS redundancy repair has not been available.…”

Section: A Yield Model For Mems Redundancy Repairmentioning

confidence: 99%

“…Further, assume every defect occurs independently of each other, and the probability for each defect to occur is equal and defined as q. Thus, based on the defect distribution discussed in [13], the probability P (X = x) that x number of indistinguishable randomly distributed defects occurring to the MEMS device can be expressed as a Poisson distribution:…”

Section: A Yield Model For Mems Redundancy Repairmentioning

confidence: 99%

“…The probability that x defects occur in a MEMS device with area A can be given by the following equation [13]:…”

Section: A Yield Model For Mems Redundancy Repairmentioning

confidence: 99%

“…The next problem is how the average defect λ distributes. In this work, we assume that the defect distribution function F (λ) for λ is a gamma function given by the following equation [13]:…”

Section: A Yield Model For Mems Redundancy Repairmentioning

confidence: 99%

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A Self-repairable MEMS Comb Accelerometer

Xiong

Jone

Advances in Computer, Information, and Systems Sciences, and Engineering

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Abstract-In this paper, a built-in self-repair technique for the MEMS comb accelerometer device is proposed. The main device of the comb accelerometer consists of n identical modules, and m modules are introduced as the redundancy. If any of the working module in the main device is found faulty during a built-in self-test (BIST), the control circuit will replace it with a good redundant module. In this way, the faulty device can be self-repaired through redundancy. The implementation of dualmode BIST on the BISR module is discussed. The sensitivity loss due to device modularization can be well compensated by different design alternatives. The yield model for MEMS redundancy repair is developed. The simulation results show that the BISR (built-in self-repair) design leads to effective yield increase compared to non-BISR design, especially for a moderate non-BISR yield. The yield as well as the reliability of the accelerometer can be improved due to the redundancy repair.

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Yield analysis for self-repairable MEMS devices

Xiong

Jone

2008

Analog Integr Circ Sig Process

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In this paper, yield analysis for a self-repairable MEMS (SRMEMS) accelerometer design is proposed. The accelerometer consists of (n + m) identical modules: n of them serve as the main device, while the remaining m modules act as the redundancy. The yield model for MEMS redundancy repair is developed by statistical analysis. Based upon the yield model, the yield increase after redundancy repair for different m and n numbers is analyzed. ANSYS Monte Carlo simulation is used to estimate the yield of BISR/non-BISR MEMS devices with random point-stiction defects. The simulation results are in good agreement with the theoretical prediction based on our yield model. The simulation results also show that the SRMEMS leads to effective yield increase compared to non-BISRS design, especially for a moderate initial yield.

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Yield increase of VLSI after redundancy-repairing

Cited by 16 publications

References 4 publications

A decoupled bit shifting technique using data encoding/decoding for DRAM redundancy repair

A decoupled bit shifting technique using data encoding/decoding for DRAM redundancy repair

A Self-repairable MEMS Comb Accelerometer

Yield analysis for self-repairable MEMS devices

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