Yield Enhancement Methodology for CMOS Standard Cells

Epinat, Arnaud; Vijayaraghavan, N.; Sautier, Matthieu; Callen, Olivier; Fabre, Sébastien; Ross, Ryan; Simon, P.; Wilson, Robin

doi:10.1109/isqed.2006.147

Cited by 1 publication

(1 citation statement)

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“…Closing the loop between the design, test and process teams involved in the production of volume circuits giving chips a unique ID with process centering data. As a result, it allows tracking on-chip process variability over fab-to-fab, wafer-to-wafer and die to die, and eases the implementation of diagnosis methodologies and yield learning [8].…”

Section: Discussion and Perspectivesmentioning

confidence: 99%

Product On-Chip Process Compensation for Low Power and Yield Enhancement

Moubdi

Maurine

Wilson

et al. 2010

Lecture Notes in Computer Science

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This paper aims at introducing a reliable on-chip process compensation flow for industrial integrated systems. Among the integrated process compensation techniques, the main one aims at reducing the supply voltage of fast circuits in order to reduce their power consumption while maintaining the specified operating frequency. The proposed design flow includes efficient methodologies to gather/sort on-chip process data but also post-silicon tuning strategies and validation methods at both design and test steps. Concrete results are introduced in this paper to demonstrate the added value of such a methodology. More precisely, it is shown that its application leads to an overall energy reduction ranging from 10% to 20% on fast chips.

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Section: Discussion and Perspectivesmentioning

confidence: 99%